Hiroaki Hazama

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

A new technique for measuring threshold voltage distribution in flash EEPROM devices

A new, simple test circuit for evaluating the reliability of flash EEPROM devices is described. It measures threshold voltage (V/sub th/) distributions of a large number of cell transistors with easy static operation similar to I-V curve measurement. Moreover, each cell transistor in a large array is selectable to measure static characteristics. This circuit makes it possible to measure the V/sub th/ distribution even in the negative region after erase operation for a NAND-type EEPROM.

Non-uniform current flow through thin oxide after Fowler-Nordheim current stress

Non-uniform current flow after Fowler-Nordheim current stress has been discussed. In a large thin oxide area, there are certain fixed spot areas which can trap electrons easily, and Fowler-Nordheim tunnel current is reduced at the spot areas. Enlargement of the stress induced leakage current due to trapped holes could happen at all spot areas with the same probability, but the spot areas are replaced easily by additional Fowler-Nordheim current stress. Each phenomenon occurs with very low probability. Using a 2M bit NOR flash EEPROM test array, non-uniform current flow occurring in a large area has been clarified by tracking all cell behavior individually.

A hot hole-induced low-level leakage current in thin silicon dioxide films

A new kind of stress-induced low-level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the gate edge. Since voltage dependence of this new kind of LLLC is steeper than that of conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in FN stress-induced LLLC. The most promising mechanism is sequential tunneling via trapped holes.

Inverter performance of 0.10 /spl mu/m CMOS operating at room temperature

The switching performance of 0.10 /spl mu/m CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 /spl mu/m gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 /spl mu/m CMOS. The switching performance of a 0.10 /spl mu/m ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 /spl mu/m ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance /spl rho//sub c/ is reduced to be less than 1/spl times/10/sup -7/ /spl Omega/ cm, further reduction of the gate overlap capacitance C/sub ov/ will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 /spl mu/m ground rule CMOS at room temperature. >

Optimization of optical properties for single-layer halftone masks

An algorithm necessary to decide the optimum optical properties of a single-layer halftone (HT) mask has been established. This paper reveals the relations between the refractive index n and the extinction coefficient k, and thickness d, and describes how to select optimum films among various materials. It has been found that SiNx is a good material for a single-layer HT mask for I-line (365 nm) and KrF (248 nm). The lithographic performance of an I-line SiNx HT mask for grouped line and space (L&S) patterns under annular illumination has also been demonstrated.

A hot carrier induced low-level leakage current in thin silicon dioxide films

A new kind of stress induced low level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the drain edge. Since the voltage dependence of this new kind of LLLC is steeper than that in the conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in the FN stress-induced LLLC. The most promising conduction mechanism is sequential tunneling via trapped holes.

Application of E-beam recrystallization to three-layer image processor fabrication

E-beam recrystallization has been applied to the fabrication of a three-layer processor. The seed structure and the E-beam conditions were successfully optimized so that a large-area SOI as wide as 1 mm was recrystallized without void generation with no damage to underlying devices. The actual SOI area in the device, 850*1100 mu m, was recrystallized with one E-beam scan by aligning its position. The three-layer image processor was capable of visual image sensing with a feature outline extraction in a parallel processing manner. Normal operations of the fundamental functions have been confirmed, demonstrating the feasibility of E-beam recrystallization for three-dimensional IC application. >

A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories

This paper describes a novel surface-oxidized barrier-SiN cell technology to effect a tenfold improvement in endurance and read disturb characteristics. In conventional memory cells, degradation of tunnel oxides due to barrier-SiN films for Self-Aligned Contact (SAC) limits the scaling of memory cells. The proposed technology overcomes this problem by an additional oxidation process subsequent to barrier-SiN deposition to reduce hydrogen in both SiN film and tunnel oxide. 0.18 /spl mu/m-rule NAND cells fabricated by the proposed technology demonstrate a tenfold improvement in allowable program/erase cycles and read disturb lifetime without any deterioration of other cell properties.

Anomalous diffusion of dopant in Si substrate during oxynitride process

Unexpectedly enormously enhanced diffusions of B and P in Si substrate during gate oxynitride process have been clarified for the first time. The apparent diffusion enhancement is observed in the reoxidation process after nitridation in NH/sub 3/ ambient. The oxidation enhanced diffusion (OED) factors of B and P are about 15 times larger than the normal OED factor, which is ascribed to the increase of interstitial Si at oxynitride/Si interface. The enormously enhanced diffusion affects the device characteristics and should be taken into account in order to perform accurate simulation for submicron MOSFETs with oxynitride gate.