Tsukasa Ooishi

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAMs to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm/sup 2/ and a performance of 34 ns access time. >

A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation.

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance. >

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs

Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V V/sub CC/. Therefore, one can make determining the V/sub th/ easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAMs with capacity of 256 Mbits and more. >

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAMs of 256 Mb and more. >

A board level parallel test and short circuit failure repair circuit for high-density, low-power DRAMs

The authors present a board level parallel test circuit which greatly increases the throughput of test operations for high-density DRAMs. Also described is a short circuit failure repair circuit which enhances the yield of super low power DRAMs. They are both useful for the manufacturing of high-density, low-power DRAMs.

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm/sup 2/ and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented.

A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs

In DRAMs a dramatic operation voltage reduction has been realized by the voltage-down converter (VDC) for a low power dissipation and high reliability. However, in the low-voltage and high-frequency domain this technique will see several crucial problems. Besides, the wide-frequency operation (e.g. an extended data output and a synchronous operation) and the variable-load current (e.g, a variable refresh cycle and a changeable data output) are required. This paper proposes VDC circuit techniques for the low-voltage (less than 2.5 V), wide-frequency, and the variable-load current. The mixed-mode VDC (MM-VDC) provides two-modes of current by the analog VDC (A-VDC) and the digital VDC (D-VDC) supply being suitable for the load current. It also reduces the current consumption in the VDC and guarantees stable operation. Moreover, the impedance adjustment circuitry (IAC) controls the current supply capability of the D-VDC according to the load operation frequency to minimize the bounce of the internal power supply level. The MM-VDC can be applicable to low-voltage wide-frequency DRAMs.

A high speed memory system based on 16 Mb ST (stretchable memory matrix) DRAMs

A multivalued addressing scheme is proposed for a high-speed, high-packaging-density memory system. A 16-Mb stretchable memory matrix DRAM (16-Mb STDRAM) is examined using this addressing design. This STDRAM with multivalued address signals achieves a 30-ns access time, a high packing density (about 70% of the address for a nonmultiplex type), a power dissipation of 121.5 mA per 80-ns cycle time, and a peak current of 59 mA. The STDRAM has the potential to realize an ultra-low-power memory system.<<ETX>>