Tsung-Fu Yang

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288degC solder dipping and 260degC level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.

Development of Cu/Ni/SnAg Microbump Bonding Processes for Thin Chip-on-Chip Packages Via Wafer-Level Underfill Film

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (μ-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <; 50 μm at the outermost region of the packaging structure without μ-bumps significantly reduces approximately 2 μm of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF.

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Evaluation of Cu/SnAg microbump bonding processes for 3D integration using wafer‐level underfill film

Purpose – 3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.Design/methodology/approach – B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy b...

Reliability assessment of the 20 um pitch micro-joints within a 3DIC assembly under various environments

For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps, sealed by a capillary underfill and then did the reliability assessment under different environments. The 4 chips have the same size of 4.6 mm by 4.6 mm by 100 um, and were assembled on one Si interposer with a dimension of 20 mm by 20 mm by 300 mm by a chip on wafer (CoW) bonder. There were more then 3000 microbumps on each chip and totally over 12,000 microbumps were on the Si interposer. The bump pitch and passivation opening of the test vehicle were 20 um and 6 um, respectively, an under bump metallization (UBM) layer of 5.0 um Cu / 3.0 um Ni was plating on Al trace and then Sn2.5Ag Pb-free solder bump with a thickness around 5.0 um was then deposited on the UBM layer. During bonding, the microjoints were formed at a peak temperature of 280°C, and the microgaps were then filled by a capillary underfill and cured at 150°C for 30 min. Subsequently, the assemblies were respectively inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of microjoints including bonding accuracy, formation of interconnections and the percentage of gas voids within the underfill. Afterwards, the test vehicles were baked at 125°C for 24 h and then stored under the test condition of 30°C / 60% RH for 192 h and finally reflowed at 260°C for 3 times to screen the samples for reliability tests, the SAM was again used to check whether the delamination defect was formed within the microgap. The reliability tests including temperature cycling test (TCT), thermal shock test (TST), high temperature storage test (HTS), pressure cooker test (PCT) and thermal humidity storage test (THST) were done according to the JEDEC standards. The results showed that the thermomechanical stress induced by TCT and TST damaged the assemblies, and the failure mode was also discussed in this investigation.

Low temperature bonding using non-conductive adhesive for 3D chip stacking with 30μm-pitch micro solder bump interconnections

Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ~ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation.

Evaluation of Cu/Ni/SnAg microbump bonding processes for thin-chip-on-chip package using a wafer-level underfill film

Three-dimension (3D) integration provides a promising approach to build complex microsystems through bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to suffer an arduous challenge as the filled gap of a large scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of mirobump joints and the relative assembly compatibility of stacked chips of 3D integrated circuits (ICs) packages are therefore deteriorated. To resolve the foregoing critical issue, a novel technology of wafer-level underfill film (WLUF) is developed. The concerned steps like alignment of WLUF coated chip to substrate chip and voids elimination to make this technology work are demonstrated. However, the co-planarity of stacked thin chips after assembling with WLUF is an urgent problem and needs to understand in detail. For this reason, this research presents a non-linear finite element analysis (FEA) with process-oriented simulated technique to estimate the warpage of stacked thin chips. On account of experimental validation, the effects of several key designed factors on the thermo-mechanical behavior of chip-on-chip package under various bonding forces are investigated. The most important findings from analytic results indicate that with a consideration of chip thickness thinner than 50μm at the outermost region of packaging structure without microbumps, a about 2μm of gap betweens chips is significantly reduced. The above-mentioned phenomenon is attributed to a major structural support at the purlieus of chip only come from WLUF is extremely weak when a uniform bonding pressures is loaded. It is also found that the following cooling procedure of WLUF would further aggravate the warpage magnitude of stacked thin chips. All the results shown in the work could be as a guideline while the bonding reliability as well as the design of structural optimization for packaging assemblies with WLUF is further improved.

Thermal and Electrical Performance Enhancement with a Cost-Effective Packaging for High Speed Memory Chips

By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant DDR II component. It can be seen that the cost advantages of PCB-like CiSP and the electrical performance of WLP can be achieved simultaneously by adopting this proposed solution. A test vehicle of DDRII-667 memory chips provided by ProMos Technologies Inc. was studied here to demonstrate the feasibility of this developed packaging. Compared with the type I CiSP and the current w-BGA package, the performance is thermally and electrically enhanced.