Jing-Yao Chang

Reliable Microjoints Formed by Solid–Liquid Interdiffusion (SLID) Bonding Within a Chip-Stacking Architecture

In this research, thousands of 20-μm pitch microbumps with a diameter of 10 μm and a structure of a pure Sn cap on a Cu pillar were electroplated on 8-inch wafers, and those wafers were then respectively singularized as a top chip and bottom Si interposer for stacking. Two methods, namely conventional reflow and solid-liquid interdiffusion (SLID) bonding, were adopted to interconnect the microbumps. In the former case, the as-plated Sn caps were fluxed, and the chip was then placed on the Si interposer. Afterward, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250 °C. The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer was fully sealed by a capillary underfill. In the SLID bonding process, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer with a bonder as well, subsequently, the Sn caps were heated to 260°C to react with the Cu pillar to form Cu6Sn5. In the final step, the intermetallic microjoints were protected by the same capillary underfill. After assembly, the Joint Electron Devices Engineering Council preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. The fracture of the microjoints was caused by the volume contraction induced by the growth of Cu6Sn5, but the failure mechanisms of those two microjoints were quite different.

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Evaluation of Cu/SnAg microbump bonding processes for 3D integration using wafer‐level underfill film

Purpose – 3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.Design/methodology/approach – B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy b...

Reliability assessment of the 20 um pitch micro-joints within a 3DIC assembly under various environments

For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps, sealed by a capillary underfill and then did the reliability assessment under different environments. The 4 chips have the same size of 4.6 mm by 4.6 mm by 100 um, and were assembled on one Si interposer with a dimension of 20 mm by 20 mm by 300 mm by a chip on wafer (CoW) bonder. There were more then 3000 microbumps on each chip and totally over 12,000 microbumps were on the Si interposer. The bump pitch and passivation opening of the test vehicle were 20 um and 6 um, respectively, an under bump metallization (UBM) layer of 5.0 um Cu / 3.0 um Ni was plating on Al trace and then Sn2.5Ag Pb-free solder bump with a thickness around 5.0 um was then deposited on the UBM layer. During bonding, the microjoints were formed at a peak temperature of 280°C, and the microgaps were then filled by a capillary underfill and cured at 150°C for 30 min. Subsequently, the assemblies were respectively inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of microjoints including bonding accuracy, formation of interconnections and the percentage of gas voids within the underfill. Afterwards, the test vehicles were baked at 125°C for 24 h and then stored under the test condition of 30°C / 60% RH for 192 h and finally reflowed at 260°C for 3 times to screen the samples for reliability tests, the SAM was again used to check whether the delamination defect was formed within the microgap. The reliability tests including temperature cycling test (TCT), thermal shock test (TST), high temperature storage test (HTS), pressure cooker test (PCT) and thermal humidity storage test (THST) were done according to the JEDEC standards. The results showed that the thermomechanical stress induced by TCT and TST damaged the assemblies, and the failure mode was also discussed in this investigation.

Characteristics of 600 V / 450 A IGBT module assembled by Ag sintering technology

Up to now, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwanese government is pushing the R&D institutes like ITRI to develop the renewable energies and smart grid technologies, and is also making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV / HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. ITRI has already achieved a 600 V / 450 A IGBT module composed of IGBTs and freewheel diodes (FWD) for EV / HEV applications. Previously, a Pb-free solder perform with a thickness of 100 μm was adopted to attach 2 IGBTs and 2 FWDs on one Al2O3 direct bonded copper (DBC) substrate in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well, by this structure, the junction temperature of the IGBT device is very close to 150°C and may deteriorate the long-term reliability. Therefore, a Ag paste sintering method was used to replace the conventional soldering process to improve the thermal dissipation and to lower the junction temperature. With an optimized process condition, a voidless die attaching joint was gained, and the die shear strength was as high as 27 MPa. Furthermore, a reduction of 22% of thermal resistance was measured by using Ag sintering, and the electrical performance of the newly developed power module was fully reported in this study.

The first MIT 600 V/450 a IGBT module for EV/HEV applications

Nowadays, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwan government is making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV/HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. The first 600 V/450 A IGBT module for EV/HEV application developed by ITRI was announced in this work. The module was composed of IGBTs and freewheel diodes (FWD), firstly 2 IGBTs and 2 FWDs were attached on one Al2O3 direct bonded copper (DBC) substrate by a Pb-free solder perform with a thickness of 100 μm in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well. After cleaning, a heavy Al wire was used to connect the devices and DBCs, and subsequently the housing was adhered to the Cu baseplate by an adhesive. Finally, a Si gel with a dielectric strength higher than 10 kV/mm was poured for insulation and then agglutinated by heating. The process conditions were optimized in this study, a die shear strength higher than 20 MPa was acquired after optimizing the reflow profile, and a design of experiments (DoEs) plan was executed to obtain a pull strength higher than 800 g for the heavy Al wire bonding. After temperature cycling for 1000 times, the loss of the strengths was less than 20%, and the long-term reliability of the power module was verified.

Dual-phase solid-liquid interdiffusion bonding, a solution for the die attachment of WBG

Wide band gap (WBG) semiconductors such as SiC and GaN devices are expected to replace Si power devices in the next generation power modules for renewable energy and smart grid to enhance their energy conversion efficiency through a characteristic of high frequency switching. However, the temperature of the WBG power module may reach 250°C as operating, which is much higher than the melting temperatures of the conventional solder materials like Sn37Pb (187°C), Sn3.0Ag0.5Cu (217°C) and Sn0.7Cu (227°C). Therefore, a new die attaching method is an urgent research subject for the assembly of WBG power modules. Sandia National Laboratories won the R&D 100 award in 2009 by the worlds first full SiC module, in which the die attaching of SiC devices was accomplished by a transition liquid phase (TLP) method, 2 intermetallic phases including Ag 3 Sn and Ni 3 Sn 4 were formed to bond SiC devices on a direct bond aluminum (DBA) and mount the DBA on a metal matrix composite baseplate, respectively, and the power module was capable to operate under a condition in excess of 400°C. Subsequently, Infineon announced a power chip embedded technology named BLADE for renewable energy applications in 2011, a same process so-called diffusion soldering was used to attach Si MOSFET device on an organic carrier by producing an intermetallic layer like Cu 6 Sn 5 between them. However, some disadvantages have been found in the previous cases. First, the bonding time is too long to achieve a high throughput production when the process temperature is lower than 300°C, whatever, the power ICs are easily damaged when the process temperature is as high as 350°C. Second, the intermetallic joint might degrade due to the voids induced by a volume contraction as heated. Third, there are some defects such as Kirkendall voids are formed at the interface between different intermetallics, which significantly impacts the reliability performance of the joint. A dual-phase solid-liquid interdiffusion bonding process was developed to solve the above-mentioned issues in this study. By the elemental design of the electrode compositions on both chip and substrate, a dual-phase intermetallic joint was formed to attach the chip on the substrate, and the bonding temperature was decreased to just 260°C. Furthermore, almost no void was found within the joint because they were rapidly stuffed by the formation of secondary intermetallic. The shear strength of the intermetallic joint was measured being higher than 20 MPa, even though experienced a temperature cycling test (Condition B, JESD22-A104), meaning that the new bonding technology was reliable and capable of manufacturing WBG power modules.

Low temperature bonding using non-conductive adhesive for 3D chip stacking with 30μm-pitch micro solder bump interconnections

Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ~ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation.

Processing characteristics and reliability of embedded DDR2 memory chips

As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution to miniaturize the size of the package. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. In addition to wire bonding or w-BGA technologies, embedded package structure provides an alternative means to form redistribution circuits and electrical bonding pads. Meanwhile the electrical performance can be enhanced due to the wafer level package-like structure. Superior electrical performance is provided by forming shorter electrical path from chip pad to outer. In this study, a chip-in-substrate package (CiSP) with a real 50 um thick DDR2 memory IC is achieved using built-up technologies such as dielectric layer lamination, micro via drilling, and redistribution layer forming to implement the JEDEC-compliant DDR2 component. The PCB compatible process is a low-cost, high-yield, and versatile technology. Electrical performance similar to wafer level package and even better than wire bonding or w-BGA package can be achieved by adopting this proposed solution. The DDR2 component is assembled on a dual in-line memory module (DIMM) to study the feasibility and electrical performance of this developed package. Subsequent reliability test such as thermal cycle test (TCT) and thermal humidity storage test (THST) are examined. And electromigration (EM) of this test vehicle under high current density is simulated and tested.