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IEEE Transactions on Electronics Packaging Manufacturing | 2001

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

Hirokazu Ezawa; Masahiro Miyata; Soichi Honma; Hiroaki Inoue; Tsuyoshi Tokuoka; Junichiro Yoshioka; Manabu Tsujimura

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 /spl mu/m by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than /spl plusmn/0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260/spl deg/C in N/sub 2/ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150/spl deg/C for 1000 h in N/sub 2/ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs.


electronic components and technology conference | 1997

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Hideo Aoki; Chiaki Takubo; Takahito Nakazawa; Soichi Honma; Kazuhide Doi; Masahiro Miyata; Hirokazu Ezawa; Yoichi Hiruta

Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less than 10% within wafer. Eutectic solder flip chip assembly process, which includes bonding, cleaning and underfilling, has been also developed. Bonding process of eutectic solder indicates good self-alignment. The excellent rosin cleaning was achieved by the ultrasonic cleaning process with Techno Care. In underfilling process, the underfill resin which can be applied to small stand-off have been chosen. Reliability tests for CSP and flip chip interconnection were carried out and confirmed the good reliability of fabrication process using eutectic solder flip chip technology.


Microelectronics International | 1997

Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps

Soichi Honma; K. Tateyama; H. Yamada; Kazuhide Doi; Naohiko Hirano; Takashi Okada; H. Aoki; Yoichi Hiruta; T. Sudo

This paper describes effective thin‐film structure barrier metals for use as eutectic solder bumps. Shear strength and bump interconnection resistance were evaluated. The mutual diffusion in metals was investigated. Barrier metal structures —Cu/Ti,Ni/Ti and Cu/Cr—were evaluated after ageing. The Ni/Ti structure has good reliability according to ageing test results. Pd is used for improvement of solder wettability and as an oxidisation barrier. Consequently, it was concluded that a thin‐film Pd/Ni/ Ti barrier metal is suitable for use as eutectic solder bumps. The broken interfaces of the solder bumps were analysed by scanning auger electron spectrometry. In the thin‐film Cu/Ti structure, decrease in the shear strength is caused by three mechanisms, as determined from the broken interface analysis. The three mechanisms are mixed metal formation, Ti oxidisation and diffusion between barrier metals and Al. Furthermore, TCT and PCT were carried out on these eutectic solder bumps to confirm the interconnection...


japan international electronic manufacturing technology symposium | 1995

Evaluation of barrier metals of solder bumps for flip-chip interconnection

Soichi Honma; Kazuki Tateyama; Hiroshi Yamada; Masayuki Saito

This paper describes the optimum thickness of barrier metals and the cause of the decrease in the shear strength of 37Pb/63Sn solder bumps for flip-chip interconnection. The authors evaluated the mutual diffusion and the shear strength of solder bumps on barrier metals. From aging test results with the Cu/Ti structure, when the thickness of the Cu film was greater than 10 /spl mu/m, the shear strength did not change from the initial value. In the Ni/Ti structure, where the Ni film had a thickness of 1.0 /spl mu/m, the shear strength also did not change from the initial value. In addition, it was confirmed that the decrease in the shear strength is caused by diffusion between Sn and Cu, or Sn and Ni, and oxidization of the barrier metals.


Archive | 1996

Semiconductor device with improved encapsulating resin

Hiroshi Yamada; Takasi Togasaki; Masayuki Saito; Soichi Honma; Miki Mori; Kazuki Tateyama


Archive | 2000

Electrode material, semiconductor device and mounting device

Soichi Honma; 荘一 本間


electronic components and technology conference | 2003

Pb-free bumping by alloying electroplated metal stacks

Hirokazu Ezawa; Masahiro Miyata; Masaharu Seto; Soichi Honma


Archive | 1996

SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF, SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Kazuhide Doi; Naohiko Hirano; Soichi Honma; Hidekazu Hosomi; Takashi Okada; Yasushi Shibazaki; Tomoaki Takubo; Hiroshi Tazawa; 一英 土井; 岡田 隆; 尚彦 平野; 荘一 本間; 康司 柴崎; 浩 田沢; 知章 田窪; 英一 細美


Archive | 2003

Semiconductor device and its assembling method

Soichi Honma; Akira Tomono; 章 友野; 荘一 本間


Journal of Japan Institute of Electronics Packaging | 2002

Sn-Ag Solder Bump Process Using 2-Step Plating Method

Masahiro Miyata; Hirokazu Ezawa; Soichi Honma; Tsuyoshi Tokuoka; Hiroaki Inoue; Junichiro Yoshioka; Manabu Tsujimura

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