Tuhin Sinha

Measurements of interfacial strengths in underfilled flip-chip electronic packages using Wedge Delamination Method (WDM)

In this work, a new wedge delamination technique for measurement of interfacial fracture strength is presented. This method can be implemented to assess the interfacial fracture behavior of underfill and silicon in flip-chip packages. Our method offers substantial advantages over traditional interfacial test methods which can be difficult to implement on brittle materials like silicon die. The efficacy of our method for interfacial strength measurements on multiple underfill-silicon interfaces will be shown in this work. A numerical framework for crack kinking at the silicon-underfill interface will also be presented. And finally, results from WDM experiments conducted at room temperature and corresponding numerical analysis will be used to compare the relative fracture strength between underfill and silicon at the flat-face and sidewall of a silicon die.

Predicting thermo-mechanical degradation of first-level thermal interface materials (TIMs) in flip-chip electronic packages

Ensuring adequate thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial thermal junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed thermal degradation and finally, a phenomenological model is developed which predicts the thermal performance of an electronic package during cyclic loading.

Review of percolating and neck-based underfills with thermal conductivities up to 3 W/m-K

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-ofthe-art capillary thermal underfill (0.7 W/m-K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry vs. wet filling of filler particles, the optimal bi-modal nanosuspension formulation and matrix material feed, and the overpressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 500 thermal cycles. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-art capillary thermal underfill.

Effect of Temperature Cycling and High Temperature Aging on the Elastic Properties and Failure Modes of Thermal Interface Materials

Highly filled thermally conductive silicone gels are routinely used as first level thermal interface materials (TIMs) between the die and lid, in flip-chip organic packages. The main challenge for these TIMs is overcoming the Coefficient of Thermal Expansion (CTE) mismatch between the die and lid materials. The TIMs must maintain excellent adhesion to both the die and lid surfaces in order to achieve and maintain optimal thermal performance. The CTE mismatch leads to increased mechanical stress and degradation of the TIM, which in turn degrades the thermal performance. In this work, the effective modulus of several TIMs was calculated by finite element modeling (FEM) in concert with mechanical testing of thin bond-line aluminum-TIM sandwiches subjected to varied stress conditions. These results are correlated to the corresponding stress die shear testing and the impact on package performance is analyzed.Copyright

A systematic experimental investigation of thermal degradation mechanisms in lidded flip-chip packages: Effects of thermal aging and cyclic loading

This research effort is geared towards establishing a robust virtual-qualification methodology for thermal performance of flip-chip packages. In the experimental analysis presented here, test vehicles were designed and tested for degradation in the module-level thermal interface material under high temperature storage (at 100C, 125C and 150C) exposure and deep thermal cycling (−40C/+125C) conditions. The experiments conducted in this study will encompass a wide range of thermo-mechanical conditions that not only explore known JEDEC variables but also provide unique insights into understanding the effects of indirect thermal degradation drivers such as package assembly loads and chip-junction temperature variations during thermal power inputs during readouts.

Geometric optimization and mechanical risk mmitigation in 2.5D flip-chip packages using parametric finite element analysis (FEA) simulations

This study is focused on geometric optimization of a 2.5D interposer based single die flip-chip package. Parametric analyses using the well-established global-local finite element method (FEM) technique have been conducted on the package at both the pre and post encapsulation (or underfill) stages. At the pre and post encapsulation phases, effects of geometric parameters which included variations in silicon die dimensions, interposer dimensions and substrate dimensions were analyzed to determine the corresponding mechanical risks associated during the die bonding and capping process. The geometric optimization at the macro-scale was focused on reducing die-underfill shear stresses and strains in the thermal interface material (TIM). At the local level, studies were geared towards understanding the impact of geometric variables on the solder inelastic strain and stresses within the back end of the line layers within the chip. The results presented from both these modeling analyses will provide configurations that reduce the overall mechanical risks in 2.5D packages and provide guidelines for geometric optimization of such packages.

A high performance Multi Component Carrier with Chip Scale Package

In this paper, we discuss the design of a four (4) chip Multi Component Carrier (MCC) package and feasibility for use in high-end server/mainframe applications. A new class of organic, Chip Scale Package (CSP) and associated design ground rules were created based on a low, coefficient of thermal expansion (CTE) organic material, in addition to the CSP form factor. Micro Ball Grid Array (BGA) is used to connect the CSP to a daughter card assembly to form the MCC package structure. The low CTE organic substrate significantly reduces the internal stress that arises from the chip to substrate bond and assembly process, which enhances the yield and reliability of the CSP and the entire MCC structure. Numerical simulation using the finite element method (FEM) has been conducted to evaluate and optimize the lid design of the MCC package in order to ensure reliable lid to package operation during assembly and field thermal excursions. Thermal and mechanical solutions with various combinations of geometric design are discussed.

Reliability Demonstration of an Ultra-Thin Core (UTC) Large Die, Large Laminate Package

The demands for the next generation organic laminate materials include high speed signal (HSS) performance enhancements as well as improvements in bond and assembly processing yields. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. The industry has recently incorporated coreless laminates mostly in small die packages to reduce layer counts and cost. However, especially for large die, large laminate form-factors, coreless packages require addressing manufacturing challenges due to warp, and concerns with chip package interaction (CPI), due to their higher coefficient of thermal expansion, CTE. A core, which provides stiffness, is beneficial to reduce high thermal warpage, especially in large body laminates. Also, to improve the mechanical performance and thermal-mechanical reliability, a lower composite laminate CTE is preferred. A low CTE core in addition allows lowering the composite CTE and is used to mitigate CPI. However, the use of thick cores increases build-up layer count due to wiring constraints and consequently increases laminate cost and thickness. Also process costs associated with laminate drilling of the plated through holes (PTH) increase. The benefit tradeoff between cored laminates and coreless can be satisfied by examining an Ultra-Thin Core (UTC) laminate package. UTC laminates offer the advantages of low cost and high speed signal transmission of a coreless laminate while overcoming its high CTE and warp concerns by utilizing a low CTE core with thickness less than 300um. Such UTC structure allows for a robust PTH formation process, developed uniquely by Kyocera. Large body size UTC laminates can be introduced into module manufacturing without any special fixturing or processing that are often needed with coreless packages. This paper focuses on the assembly, characterization, and reliability stress results of UTC laminates used to assemble large die, large laminate (LD/LL) SCM packages. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is proportional to the DNP (distance from neutral point) and therefore solder fatigue fails often occur at the corner C4s first. Higher laminate composite CTE imposes additional shear strain to the C4 interconnect bumps. The UTC core helps to reduce the composite CTE and improve reliability. The flip chip package studied was a 6-2-6, 55mm laminate structure with 200um core and solder resist opening defined C4 bumps. Comparison is made with a 6-2-6, 55mm laminate with 400um core (thin core) and C4 solder resist opening. A CPI test chip was mounted on the low CTE UTC Ball Grid Array (BGA) laminate using traditional bond and assembly (BA) processes and fixtures. This was followed by liding with a Thermal Interface Material (TIM) between the test chip and a heat spreader, and an elastomer sealant between the laminate and the heat spreader. The sub-assembly was then tested, attached to a thermal card for power and signal connection. Examination of the C4 interconnect after 1000 cycles of deep thermal cycling (DTC) and biased Highly Accelerated Stress Test (HAST) of 110°C, 85% Relative Humidity (RH), and 3.6 volt bias revealed good C4 interconnect reliability of UTC laminate packages, comparable to the traditional 400um core laminates. Characterization and construction analysis of the package, and model and data comparison with traditional thin core and coreless packages will be presented.

Effect of Underfill Formulation on Large-Die, Flip-Chip Organic Package Reliability: A Systematic Study on Compositional and Assembly Process Variations

Selection of appropriate underfills (or encapsulants) for flip-chip packages is critical to their reliability. In this research article, we present a comprehensive study geared towards the development of such materials. Several underfill formulations were developed based on the target material property guidelines obtained from parametric numerical simulations. Material parameters such as base resin composition, filler particle size, filler particle surface treatment and adhesive strength were modulated to arrive at an optimal composite material composition which facilitated package assembly. The robustness of these formulations was further evaluated by conducting post-assembly thermal cycling tests. Results on the reliability performance of these tailor-made underfills along with the failure analysis studies and correlation with numerical modeling will be presented.

Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package

BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. A typical organic laminate structure consists of one or more layers of build-up and copper on each side of a copper clad core. In recent years, the industry has also introduced the concept of organic build up laminate without a core layer, more commonly known as coreless laminates, to overcome the disadvantages of the plated through holes (PTH) in the core structures, which specifically drive restrictions in wiring capability and retard signal transmission speed. Although coreless laminates offer better opportunity for low cost and high speed transmission package designs, they are usually associated with high thermal warpage due to the lack of reinforcement provided by a rigid core layer. This becomes particularly challenging in large body size substrates. Furthermore, the composite coefficient of thermal expansion (CTE) of a coreless laminate is significantly higher than cored alternatives, which leads to higher chip package interaction (CPI) stresses. This paper focuses on the reliability issues of C4 bump cracking in a large die large laminate (LDLL) coreless flip chip package. C4 solder bumps are subjected to shear strains and fatigue degradation during thermal cycling and power cycling in field operation. Such shear strain is normally proportional to the DNP (distance from neutral point). Therefore solder fatigue often occurs at the corner C4s first. To further increase the reliability concern, the composite CTEs of coreless organic laminates are higher than cored laminates, which impose additional shear strain to the C4 interconnect bumps. Two coreless flip chip packages, with pad defined C4 bumps and solder mask opening defined C4 bumps, will be examined in this paper. Comparison of fail counts after 1000 cycles of deep thermal cycling (DTC) reveals that pad defined C4 bumps are more robust than solder mask opening defined C4s. Failure analysis of the cracked C4 bumps will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. Parametric studies on the effect of C4 bump geometry, laminate material properties and other form factors on C4 fatigue will be discussed. A predictive model for C4 solder joint fatigue in coreless flip chip packages will be proposed.