Tung-Hsing Lee

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices

Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure

Effects of the poly gate finger pitch on, hot-carrier-nduced reliability degradation, and radio frequency characteristics of the 40-nm n-channel metal-oxide-semiconductor field-effect transistors with contact-etch-stop-layer (CESL) strain and multifinger gate structures were systematically investigated by both experiment and technology computer-aided design simulation. The finger pitch influences both the transfer of CESL-induced stress into a channel and the shadow effect of a poly gate on a pocket implantation. The results showed that the effects of the poly gate finger pitch were more obvious for pitches less than 0.12 . Additionally, the change in stress on the channel was dominant for pitches larger than 0.12 , but for pitches less than 0.12 , the modulation of pocket implantation shadow effects became the main controlling factor.

PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

Effect of STI stress on leakage and Vccmin of a sub-65 nm node low-power SRAM

In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and Vccmin of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and Vccmin of the devices in a 65 nm node SRAM cell significantly.

A Novel Method to Improve Laser Anneal Worsened Negative Bias Temperature Instability in 40-nm CMOS Technology

From the measured data, the impact of the rapid thermal process (RTP) and laser spike anneal (LSA) sequence on negative bias temperature instability (NBTI) and current gain was investigated on 40-nm complementary metal-oxide semiconductor technology. For the conventional sequence RTP/LSA, a significant threshold voltage VT shift is observed due to the NBTI. The thermal gradient in the LSA step induces a thermomechanical stress inducing oxide fixed charges and an increase in Si dangling bonds at the SiON/Si interface, thus increasing the VT shift. By moving the LSA step to before the RTP anneal and coimplanting a carbon atom in the source/drain extension implant processing, the obvious VT shift could be suppressed to the same as the RTP-only anneal. Best of all, the sequence change does not impact the gain of the original combination anneal over the RTP-only anneal in the on current of devices.

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

Effect of etch stop layer stress on negative bias temperature instability of deep submicron p-type metal-oxide-semiconductor field effect transistors with dual gate oxide

Negative bias temperature instability (NBTI) in a dual-gate-oxide complementary metal–oxide–semiconductor (CMOS) process induces threshold voltage (Vt) shift and has become a crucial challenge in designing advanced analog or mixed-signal circuits. In this paper, the impact of the stress from a contact etch stop layer (CESL) on the NBTI of dual-gate-oxide input/output (I/O) p-type MOS field effect transistors (P-MOSFETs) is investigated in detail. Experimental results show that applying tensile stress can suppress NBTI-induced Vt shift more significantly than applying compressive stress, thus becoming a simple and effective method of relieving NBTI.

A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the NixSi FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance ION. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the ION of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data

Capping layer induced degradations in nano MOSFETs with scaled IL

EOT scale down is a critical issue in LaO/AlO capped Hf-based devices, because it will result in serious VFB roll-off. The incorporation of capping layer induces more traps in the gate stack. These traps are oxygen vacancy related defects and are sensitive to reliability stress. By using the oxygen vacancies detection method, we demonstrate that these oxygen vacancy defects are near to IL (SiO2). In addition, the interface states are found strongly dependent on the VFB roll-off, especially for IL scaled device.

Mechanism and modelling of source/drain asymmetry variation in 65?nm CMOS devices for SRAM and logic applications

The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM.