Tushar P. Merchant

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

16Mb Split Gate Flash Memory with Improved Process Window

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

A Predictive Model for Controlling Wafer Level Polish Rate Uniformity in Oxide CMP

A stress based engineering model has been developed that predicts the removal rate profile across the wafer as a function of the principal and shear stresses on the wafer. The model reproduces the form of the radial variation in polish rate that is seen without back side air for the current set of consumable conditions and the changes in the polish rate profile that occur when back side air pressure is used on an IPEC-472 tool. The model which is GUI based and can be run in the fab, returns the optimum recipe setting to maximize polish rate uniformity based on the current tool performance. Implementing this model in production resulted in a 50% improvement in within wafer uniformity statistics.