Rajesh A. Rao

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

16Mb Split Gate Flash Memory with Improved Process Window

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

Silicon Nanocrystal Nonvolatile Memory

Silicon nanocrystal memory devices [1],[2] such as shown in Fig. 4.1, offer the potential to solve the challenging problem of scaling nonvolatile memories. Scaling of floating-gate (FG) nonvolatile memory cells has been limited to bottom oxide thicknesses in the range of 80–110 A primarily because of the vulnerability to charge loss from the conducting FG through isolated defects in the tunnel oxide that arise after repeated write/erase operations. As a result the FG, operating voltages are in the range of 16–20 V required for erasing the memory cell by Fowler-Nordheim tunneling of carriers from the FG to the channel. This voltage is sometimes split as ±8 to ±10 V using fully isolated wells. Silicon nanocrystal memory cells that store charge in isolated centers inside a gate dielectric are less susceptible to charge loss through isolated defect paths in the tunnel oxide due to their discontinuous nature of charge storage. In other words, an underlying oxide defect leads to charge loss only from charge storage sites in its immediate proximity. Once the impact of defect-mediated charge loss is mitigated, charge loss is primarily due to tunneling and the tunnel oxide in these devices can be scaled down to about 50–60 A based on retention-time requirements. The scaling of the tunnel oxide results in embedded memory modules that can operate with a maximum on-chip voltage of ±6 V, allowing reduction of the memory module size by up to a factor of 2 at the 90-nm technology node, as shown in Fig. 4.2 [3]. Furthermore, this reduction in operating voltage enables sharing of logic I/O device implants with the high-voltage periphery devices, which are used to charge and discharge the memory bitcells in the array. Open image in new window FIGURE 4.1 Silicon nanocrystal nonvolatile memory bitcell showing the floating silicon nanocrystals used for isolated charge storage. A cross-section transmission electron microscopic image through the gate stack of a bitcell and a plan view scanning electron microscopic image of the nanocrystals is also shown. Open image in new window FIGURE 4.2 Memory module size for both conventional FG nonvolatile memory (NVM) and nanocrystal-based NVM showing the approximate factor-of-2 reduction in memory module size for nanocrystal-based NVM.