Tzu-Heng Chang

An on-chip combo clamp for surge and universal ESD protection in bulk FinFET technology

A surge protection consisted of the ready-made ESD clamp transistors has been designed and characterized in FINFET technology. It can endure all the stresses from CDM, HBM and Surge events. Compared to a conventional 0.7V RC-based core ESD clamp, the proposed cell greatly boosts the Surge immunity from 4V to 19V.

An analog front-end circuit with dual-directional SCR ESD protection for UHF-band passive RFID tag

In this study, we demonstrate an analog front-end (AFE) circuit with ESD protection for a passive RFID tag at UHF-band (860∼960 MHz) in a 0.18-μm CMOS technology. A dual-directional silicon-controlled-rectifier (dual-SCR) structure is proposed for the ESD protection under the large-signal operation at the RFID input. With the well-designed dual-SCR, a large trigger voltage (VT) of ∼ 16.9 V is obtained. The parasitic capacitance of the ESD block is only ∼ 34 fF, which has virtually no impact on the core circuits at the frequency of interest. The measured ESD levels achieve 3.0-kV human-body-mode (HBM) and 200-V machine-mode (MM), respectively. The RF-DC rectifier in the RFID circuit can generate a stable power supply output about 1.2 V when the RF input power exceeds −7.5 dBm.

Deep N-well induced latch-up challenges in bulk FinFET technology

DNW-induced latch-up characteristics and their temperature-dependence are investigated in bulk FinFET technology. DNW-enclosed NMOS in PNPN and PNPNPN structures causes low latch-up immunity with detrimental high-temperature degradation. Varied methods are explored for holding voltage improvement. In summary, the shunting-resistance reduction through process-design co-optimization plays a critical role in solving DNW-induced latch-up challenges in FinFET technology.