Uli Kretzschmar

Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs

Developing safety-aware designs on field programmable gate arrays (FPGA) directly feeds a demand for error emulation techniques. Since for SRAM-based FPGA single event upsets (SEU) are the most important concern, error testing is usually executed using error injection into the configuration memory. This error injection is typically done with either external or internal injection with the corresponding drawback of slow injection speeds or inaccurate results due to injection side effects. In this context, this work introduces a complete test flow with a mathematical framework and injection parameters which allow balancing the tradeoff between quality of the results and injection speed. An implementation of this flow is presented and executed on a case study based on an AES encryption application. The flows implementation has a very low resource overhead, which can be almost negligible in some instances. Therefore, it can be included in a final implementation allowing for robustness measurements of the finally placed and routed design.

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS

This paper introduces an experimental test-flow for evaluating the susceptibility of SRAM based FPGA designs to SEU (Single Event Upsets). Using this method it is possible to cover both SEUs and MBU (Multiple Bit Upsets) in the configuration memory of Xilinx FPGAs for applications based on tiny soft microprocessors. The introduced test-flow imposes a minimal effort to the system developer and achieves a good estimation on the percentage of critical bits in the configuration memory of a design. This flow is executed for a design using multiple tiny soft microprocessors and the reliability values extracted by the test-flow are compared to non-experimental estimation techniques.

SHA-3 based Message Authentication Codes to secure IEEE 1588 synchronization systems

Since the publication of IEEE 1588-2008 standard, the interest in giving cyber-security to Precision Time Protocol (PTP) traffic has increased. Therefore, several researches regarding security vulnerabilities and possible implementation improvements can be found in the literature. Particularly, SHA-1 and SHA-2 based MAC algorithms specified in the standard have already been proved to be suboptimal. In this paper, the utilization of new SHA-3 based MAC is proposed and both AES-128 and SHA-3 hardware implementations are compared in the context of PTP networks.

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA

Triple Module Redundancy (TMR) is a popular technique for protecting critical FPGA designs. Although automatic tools for TMR generation mostly use triplication on flip-flop level, designers may opt for different approaches. This work analyses the impact of different granularities on TMR architectures based on a coarse- and a medium-grained TMR implementation of a shared Wishbone interconnection. The actual robustness of these different implementations is measured on a Xilinx Virtex-5 FPGA by using error injection into the configuration bitstream. A specialized test setup comprising two FPGAs boards is introduced so as to allow for the execution of the robustness testing. Based on the coarse-grained architecture, a fine categorization of errors in TMR architectures can be obtained.

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Common features for comparing AES implementations are the latency and throughput of the module as well as its resource requirements. This work evaluates the robustness against punctual errors in the FPGA caused by SEUs or other effects for a variety of AES implementations in order to provide a possible additional feature differentiating various architectures. The AES implementations included in this work span from a speed of more than one Mcycle for one encryption to 16 cycles per encryption. A fault injection flow is executed on the different implementations in order to determine their robustness against these punctual errors.

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.

Securing IEEE 1588 messages with message authentication codes based on the KECCAK cryptographic algorithm implemented in FPGAs

Having a common sense of time is a key factor for many Smart Grid functions, such as the Sampled-Value (SV) process bus operation. The IEC 61850 family of standards recommends the Precision Time Protocol (PTP) for substation communication networks. This protocol allows accuracies in the nanoseconds range using conventional Ethernet networks. But security is only defined as an optional extension and presents several vulnerabilities. In particular, the cryptographic algorithms specified in the standard are suboptimal due to latency and area cost and hence, in this paper, the implementation of the new SHA-3 based MAC in programmable devices is proposed to improve the impact of security on PTP performance.

Fast and accurate SEU-tolerance characterization method for Zynq SoCs

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a “Xilinx Zynq®-7000 All Programmable System on Chip (SoC)” device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. This interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. This method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches.

Interface tasks oriented 8-bit soft-core processor

The utilization of embedded soft-core processors in electronic systems offers multiple benefits such as better performance, cost reduction, flexibility and design innovation. This paper describes the architecture and implementation of an 8-bit embedded processor for SRAM-based FPGA (Field Programmable Gate Array) systems oriented to interface tasks. The processor architecture is based on the PIC16 architecture, with several optimizations obtaining the FPGA area usage reduction, plus an ease of use. In this way, the processor developed in this work is especially suitable for a number of interface tasks that do not require a large high processing throughput, achieving a saving in the use of resources. The design has been synthesized in a Xilinx Virtex-5 FPGA using the Xilinx ISE 13.4 design suite. The validation of the processor has been executed by implementing a serial transmitter, as an interface application example. Finally, the core has been compared with the PPX16 core.