Armando Astarloa

Malguki: an RSSI based ad hoc location algorithm

Abstract The problem of finding the location of a node in wireless networks has been a research interest in the last years. In environments where the GPS does not work, the estimation of a node position using only RF signals is not a trivial task. Although some other systems have been proposed so far, using ultrasonic signals, IR, etc. But those require additional hardware that is only to be used for location finding. This article describes an algorithm, which computes the location of a node using noisy distance estimations. Thus, the restriction on distance exactitude can be relaxed and RF signal based distance estimations may be used to estimate the node location.

A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

This paper presents a new Single Event Upset (SEU), Multiple Bit Upset (MBU) and Single Hardware Error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional TripleModule Redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable TMR architecture, designed under both spatial and implementation diversification premises. Moreover, since the strategy works on the devices bitstream domain, the basis for Virtex-4 FPGAs bitstream definition are also shown.

Using Software Defined Networking to manage and control IEC 61850-based systems

Display Omitted We describe the IEC 61850 communication model and provide an SDN-based framework.This framework mainly uses the OpenFlow, sFlow, and OVSDB protocols.It controls an IEC 61850 network, including resource analysis and management.It integrates traffic engineering techniques, such as QoS or traffic filtering. Smart Grid makes use of Information and Communications Technology (ICT) infrastructures for the management of the generation, transmission and consumption of electrical energy to increase the efficiency of remote control and automation systems. One of the most widely accepted standards for power system communication is IEC 61850, which defines services and protocols with different requirements that need to be fulfilled with traffic engineering techniques. In this paper, we discuss the implementation of a novel management framework to meet these requirements through control and monitoring tools that provide a global view of the network. With this purpose, we provide an overview of relevant Software Defined Networking (SDN) related approaches, and we describe an architecture based on OpenFlow that establishes different types of flows according to their needs and the network status. We present the implementation of the architecture and evaluate its capabilities using the Mininet network emulator.

Overview of FPGA-Based Multiprocessor Systems

Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes it possible to implement complete multiprocessor systems in a single FPGA. It allows fast design, implementation and testing of new devices. This paper presents an overview of FPGA-based multiprocessor systems. It describes the main characteristics, comments on several FPGA-based multiprocessor systems appearing in the research community in the last 5 years and discusses some of the challenges in this field.

Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications

Abstract Every month new applications of fuzzy logic to image processing appear. The lightly tight nature of fuzzy algorithms simulates human vision and thus, the field of applications widens. This paper implements in hardware a very popular fuzzy algorithm, the Fuzzy C-Means algorithm. The version of the algorithm allows a high degree of parallelism, which makes the hardware implementation suited for real-time video applications.

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs

In this work we present a self-reconfiguration control focused on multiprocessor core-based systems implemented on FPGA technology. An infrastructure of signals, protocols, interfaces and a controller is exposed to perform safe hardware/software reconfigurations. This infrastructure is part of the Tornado framework that includes other elements such as a multi-context assembler for a reconfigurable processor or a custom design flow developed for the Wishbone IP-Core interconnection specification. We present two applications where the presented control system has been applied, and it is compared with other available approaches.

Reconfigurable multiprocessor systems: a review

Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

Neuro semantic thresholding using OCR software for high precision OCR applications

This paper describes a novel approach to binarization techniques. It presents a way of obtaining a threshold that depends both on the image and the final application using a semantic description of the histogram and a neural network. The intended applications of this technique are high precision OCR algorithms over a limited number of document types. The input image histogram is smoothed and its derivative is found. Using a polygonal version of the derivative and the smoothed histogram, a new description of the histogram is calculated. Using this description and a training set, a general neural network is capable of obtaining an optimum threshold for our application.

Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs

Developing safety-aware designs on field programmable gate arrays (FPGA) directly feeds a demand for error emulation techniques. Since for SRAM-based FPGA single event upsets (SEU) are the most important concern, error testing is usually executed using error injection into the configuration memory. This error injection is typically done with either external or internal injection with the corresponding drawback of slow injection speeds or inaccurate results due to injection side effects. In this context, this work introduces a complete test flow with a mathematical framework and injection parameters which allow balancing the tradeoff between quality of the results and injection speed. An implementation of this flow is presented and executed on a case study based on an AES encryption application. The flows implementation has a very low resource overhead, which can be almost negligible in some instances. Therefore, it can be included in a final implementation allowing for robustness measurements of the finally placed and routed design.

Hardware architecture for a general regression neural network coprocessor

This article presents a series of hardware implementations of a general regression neural network (GRNN) using FPGAs. The paper describes the study of this neural network using different fixed and floating point implementations. The implementation includes training as well as testing of the network. It is focused on precision loss and area and speed results of the resulting neural network coprocessor that can be used in a System on Programmable Chip. A GRNN is able to approximate functions and it has been used in control, prediction, fault diagnosis, engine management among others. They are mainly implemented as software entities because they require a great amount of complex mathematical operations. With the increasing power and capabilities of current FPGAs, now it is possible not only to translate them into hardware but, due to the reconfigurable feature of these devices, to explore different hardware/software partitions as well. These hardware implementations increase both the speed and performance of these neural networks and the designer can select the area-speed trade-off that best fits the application.