Jaime Jimenez

Overview of FPGA-Based Multiprocessor Systems

Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes it possible to implement complete multiprocessor systems in a single FPGA. It allows fast design, implementation and testing of new devices. This paper presents an overview of FPGA-based multiprocessor systems. It describes the main characteristics, comments on several FPGA-based multiprocessor systems appearing in the research community in the last 5 years and discusses some of the challenges in this field.

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs

In this work we present a self-reconfiguration control focused on multiprocessor core-based systems implemented on FPGA technology. An infrastructure of signals, protocols, interfaces and a controller is exposed to perform safe hardware/software reconfigurations. This infrastructure is part of the Tornado framework that includes other elements such as a multi-context assembler for a reconfigurable processor or a custom design flow developed for the Wishbone IP-Core interconnection specification. We present two applications where the presented control system has been applied, and it is compared with other available approaches.

Reconfigurable multiprocessor systems: a review

Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

A top-down design for the train communication network

A new electronic design for a TCN (train communication network) bus is presented in this paper. Based on top-down philosophy and focused on system on a chip strategies, various of its modules are expected to be reused in some other designs for complex communication circuits. In order to verify the Class 1 device proposed for MVB (multifunction vehicle bus), its final description has been synthesized. The advantages and problems encountered are described. The process proposed to refine system description is based on these three models: an algorithmic model using a high level language, a functional model in VHDL and the final model for synthesis, also in VHDL. The simulation and verification process has been accounted from the initial algorithmic model, so much time has been saved. Translation between algorithmic and functional models is straightforward because both descriptions have been intentionally made similar, but much care must be taken to take advantage of concurrency in HDL. The last model for synthesis conversion is based on structural division, by making smaller blocks from the functional description. Exhaustive simulation using specific testbenches has validated each model. Although design flow is generic enough to be used in other cases, such a device is a good test for this methodology. Bottom-up design methodology and a multichip approach were used during an initial experience in MVB device synthesis.

Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs

Developing safety-aware designs on field programmable gate arrays (FPGA) directly feeds a demand for error emulation techniques. Since for SRAM-based FPGA single event upsets (SEU) are the most important concern, error testing is usually executed using error injection into the configuration memory. This error injection is typically done with either external or internal injection with the corresponding drawback of slow injection speeds or inaccurate results due to injection side effects. In this context, this work introduces a complete test flow with a mathematical framework and injection parameters which allow balancing the tradeoff between quality of the results and injection speed. An implementation of this flow is presented and executed on a case study based on an AES encryption application. The flows implementation has a very low resource overhead, which can be almost negligible in some instances. Therefore, it can be included in a final implementation allowing for robustness measurements of the finally placed and routed design.

Real-Time Stereo Vision Processing System in a FPGA

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo vision algorithms. We show the results of the synthesis and its implementation cost in logic elements and time delays. The synthesis results have been implemented in a practical prototype

Design of a Master Device for the Multifunction Vehicle Bus

This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.

Comparison of two designs for the multifunction vehicle bus

In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one ranges from 1.90 to 4.12, depending on the synthesis tool and the device. Selecting as reference the tool and field-programmable gate array (FPGA) that use the fewest logical elements, the bottom-up design can work 2.3 times faster than the top-down one, after two and three iterations for the physical implementation, respectively. In both cases, the circuit has been synthesized on a Virtex-E XCV3200E of Xilinx by Xilinx Synthesis Tool (XST), so that there has been no shortage of physical resources. Therefore, for a particular pair of synthesis tool and device, the final implementation is determined by the design style and not by a hard placement and routing in a hostile fabric. After synthesis, the top-down design was 23.37% larger than the bottom-up design, so the results are not as poor as expected from a nonstructured design; however, this percentage, which is always positive, depends very strongly upon the particular synthesis tool and FPGA. In addition, both descriptions have been completely implemented in a similar CPU time (even the top-down one slightly more quickly, at the first attempt). So the top-down design style is a good candidate to produce circuits in a short time to market (in this case 28% lower), although synthesis tools must be improved in order to increase the performance.

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS

This paper introduces an experimental test-flow for evaluating the susceptibility of SRAM based FPGA designs to SEU (Single Event Upsets). Using this method it is possible to cover both SEUs and MBU (Multiple Bit Upsets) in the configuration memory of Xilinx FPGAs for applications based on tiny soft microprocessors. The introduced test-flow imposes a minimal effort to the system developer and achieves a good estimation on the percentage of critical bits in the configuration memory of a design. This flow is executed for a design using multiple tiny soft microprocessors and the reliability values extracted by the test-flow are compared to non-experimental estimation techniques.

Study on communication technologies for the optimal operation of smart grids

The traditional electrical grid must evolve to an intelligent smart grid SG to achieve efficiency, reliability, environmental and power quality improvements. Communication techniques and protocols will be crucial to manage the SG. This paper studies the communication requirements for SGs and describes the most suitable communication protocols, wired and wireless, with special attention to the latest proposals in this field. The security issues derived from data transmission through electrical grids are also analysed with a deep description of the current best practices employed to assure the SG protection face to intrusions. Copyright