Aitzol Zuloaga

Hardware implementation of optical flow constraint equation using FPGAs

This paper describes the hardware implementation of a high complexity algorithm to estimate the optical flow from image sequences in real time. Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work, a specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hard-ware has many applications in fields like object recognition, image segmentation, autonomous navigation, and security systems. The final system has been developed with hardware that combines FPGA technology and discrete FIFO memories.

Malguki: an RSSI based ad hoc location algorithm

Abstract The problem of finding the location of a node in wireless networks has been a research interest in the last years. In environments where the GPS does not work, the estimation of a node position using only RF signals is not a trivial task. Although some other systems have been proposed so far, using ultrasonic signals, IR, etc. But those require additional hardware that is only to be used for location finding. This article describes an algorithm, which computes the location of a node using noisy distance estimations. Thus, the restriction on distance exactitude can be relaxed and RF signal based distance estimations may be used to estimate the node location.

LL-MAC: A low latency MAC protocol for wireless self-organised networks

This paper proposes LL-MAC, a medium access control (MAC) protocol specifically designed for wireless sensor network applications that require low data latency. Wireless sensor networks use battery-operated computing and sensing devices and their main application is environmental monitoring. In order to achieve such requirements, the whole network must work autonomously and collaborate in periodically sensing the surrounding environment and sending data to the sink. LL-MAC uses novel techniques to offer a low end-to-end data transmission latency from the furthest away nodes to the sink in a unique working cycle while offering a low duty cycle operation in a multi-hop fashion. Key features of this protocol include a synchronised sleep schedule to reduce control overhead along with a mechanism to avoid overhearing unnecessary traffic and elude collisions. Finally, control interval adjustment enables power-aware topology management in changing environments.

Hardware architecture for optical flow estimation in real time

Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. A specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hardware may have many applications in fields like object recognition, image segmentation, autonomous navigation and security systems. To simulate image processing models described in VHDL an application specific test bench has been designed.

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs

In this work we present a self-reconfiguration control focused on multiprocessor core-based systems implemented on FPGA technology. An infrastructure of signals, protocols, interfaces and a controller is exposed to perform safe hardware/software reconfigurations. This infrastructure is part of the Tornado framework that includes other elements such as a multi-context assembler for a reconfigurable processor or a custom design flow developed for the Wishbone IP-Core interconnection specification. We present two applications where the presented control system has been applied, and it is compared with other available approaches.

Real-Time Stereo Vision Processing System in a FPGA

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo vision algorithms. We show the results of the synthesis and its implementation cost in logic elements and time delays. The synthesis results have been implemented in a practical prototype

SOM Segmentation of gray scale images for optical recognition

This paper describes a clustering technique using Self Organizing Maps and a two-dimensional histogram of the image. The two-dimensional histogram is found using the pixel value and the mean in the neighborhood. This histogram is fed to a self organizing map that divides the histogram into regions. Carefully selecting the number of regions, a scheme that allows an optimum optical recognition of texts can be found.The algorithm is specially suited for optical recognition application where a very high degree of confidence is needed. As an example application, the algorithm has been tested in a voting application, where a high degree of precision is required. Furthermore, the algorithm can be extended to any other thresholding or clustering applications.

Hardware architecture for a general regression neural network coprocessor

This article presents a series of hardware implementations of a general regression neural network (GRNN) using FPGAs. The paper describes the study of this neural network using different fixed and floating point implementations. The implementation includes training as well as testing of the network. It is focused on precision loss and area and speed results of the resulting neural network coprocessor that can be used in a System on Programmable Chip. A GRNN is able to approximate functions and it has been used in control, prediction, fault diagnosis, engine management among others. They are mainly implemented as software entities because they require a great amount of complex mathematical operations. With the increasing power and capabilities of current FPGAs, now it is possible not only to translate them into hardware but, due to the reconfigurable feature of these devices, to explore different hardware/software partitions as well. These hardware implementations increase both the speed and performance of these neural networks and the designer can select the area-speed trade-off that best fits the application.

High availability automation networks: PRP and HSR ring implementations

The work developed has as basis the networks/protocols described in the standard IEC 62439-3 Industrial automation networks - High availability automation networks: PRP and HSR. The similarities of both networks and a software implementation over Linux of PRP protocol have been the starting points taken for this work. A prototype of a HSR node has been developed; this prototype was proved over some virtual machines connected in a ring network as the standard states and achieved the target of seamless availability. Then it has been ported over an FPGA to validate the system in a FPGA/PC heterogeneous network.

Design of a Master Device for the Multifunction Vehicle Bus

This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.