Usman A. Mughal

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

Global modeling of spatially distributed microwave and millimeter-wave systems

Microwave and millimeter-wave systems have generally been developed from a circuit perspective with the effect of the electromagnetic (EM) environment modeled using lumped elements or N-port scattering parameters. The recent development of the local reference node concept coupled with steady-state and transient analyses using state variables allows the incorporation of unrestrained EM modeling of microwave structures in a circuit simulator. A strategy implementing global modeling of electrically large microwave systems using the circuit abstraction is presented. This is applied to the modeling of a quasi-optical power-combining amplifier.

Object oriented microwave circuit simulation

An object-oriented microwave circuit simulation environment is described. The design of the program is intended to offer flexibility without sacrificing efficiency. Recent developments in object-oriented techniques and in C++ compilers are used to obtain a flexible and robust system ideally suited to the development of a global modeling strategy for the integration of circuit, field, thermal, and mechanical analyses. The simulation of spatial power combining systems is used as a vehicle to illustrate the architectural developments of the system.

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Traditional inaccuracies during manufacturing test of the thermal sensor circuit require excessive guard-bands. These guard-bands increase the chance of unnecessary microprocessor throttling and could introduce a less-than optimum power and thermal design envelope. Circuit techniques that minimize these errors are discussed, including an improved temperature-independent voltage pump, a remote thermal sensing scheme for hot-spot to sensor offset reduction, and a self-heating error calibration method. Experimental data obtained on a high performance 65nm Intel® Pentium® 4 microprocessor demonstrates the feasibility and effectiveness of these techniques, providing a combined potential accuracy improvement of up to 17°C.

A full-wave system simulation of a folded-slot spatial power combining amplifier array

An integrated electromagnetic and circuit modeling environment is developed for a CPW-based spatial power combining array with folded slot antennas. The simulation and measurements of the effective isotropic power gain (EIPG) of an individual cell and of a 4/spl times/4 array is presented.

A design for test technique for parametric analysis of SRAM: on-die low yield analysis

Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.