Uzma Rana

Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution

We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length LG = 30 nm. Our best short-channel devices exhibit peak saturation transconductance GMSAT = 1140 μS/μm at LG = 60 nm and supply voltage VDD = 0.5 V.

CMOS-Compatible Self-Aligned In 0.53 Ga 0.47 As MOSFETs With Gate Lengths Down to 30 nm

We demonstrate self-aligned fully-depleted 20-nm-thick In_0.53Ga_0.47As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L_G down to 30 nm, low series resistance R_EXT = 375 Ω·μm, and high peak saturation transconductance G_MSAT = 1275 μS/μm at L_G = 50 nm and drain bias V_DS = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μ_EFF = 650 cm²/Vs at sheet carrier density N_S = 5 × 10¹² cm^-2. Finally, using a calibrated quasi-ballistic FET model, we argue that for L_G ≤ 20 nm, μ_EFF ≈ 1000 cm²/Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.