Joel P. de Souza

CMOS-Compatible Self-Aligned In 0.53 Ga 0.47 As MOSFETs With Gate Lengths Down to 30 nm

We demonstrate self-aligned fully-depleted 20-nm-thick In_0.53Ga_0.47As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L_G down to 30 nm, low series resistance R_EXT = 375 Ω·μm, and high peak saturation transconductance G_MSAT = 1275 μS/μm at L_G = 50 nm and drain bias V_DS = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μ_EFF = 650 cm²/Vs at sheet carrier density N_S = 5 × 10¹² cm^-2. Finally, using a calibrated quasi-ballistic FET model, we argue that for L_G ≤ 20 nm, μ_EFF ≈ 1000 cm²/Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.

Comparison of back interface structure alternatives using two sided optical excitation

The back interface of a solar cell is an important part of the device structure, providing several important functions: 1) reduces the effective surface recombination velocity, therefore raises both the short circuit current and Voc; 2) it may contain a high-low junction which adds its own contribution to the Voc and Vmax; 3) provides a low resistance ohmic contact. An added optical effect includes reflectance of long wavelength light back into the semiconductor not absorbed on the first pass through the material. The most common back interface structure is a “back surface field” created by a high - low junction. Others include a passivated surface using dielectrics such as SiO2, SiN, or Al2O3, a floating junction inbetween localized contacts, and a local BSF where a h-l junction is present between passivated regions. This paper focuses on the contribution to Voc made by the h-l junction.

Strained High Percentage (60%) Boron Doped Silicon-Germanium Alloys - Strain, Dopant Substitionality, Carrier Concentration, Resistivity, and Microstructure Development

In this work we study the incorporation of boron into fully strained high percentage (60%) boron doped Silicon-Germanium (SiGe). We will discuss the epitaxial growth, dopant incorporation, and strain compensation due to the dopant atoms, defect generation in highly strained doped SiGe layers as well as dopant activation, free carrier concentration and mobilities. We will look at band structure effects due to high doping in strained SiGe layers.

Advanced Applications of Semiconductor Epitaxy for Cutting Edge Integrated Circuit Technolgy

Silicon and silicon germanium epitaxy is playing a pivotal role in current CMOS technology. The application of semiconductor epitaxy in the past was mainly confined to hetero junction bipolar technology (HBT) to control boron doping profile in the base region, and to provide p Si layer for CMOS. However, as CMOS scaling is becoming increasingly difficult, exploitation of strain-Si in the channel region to boost CMOS performance has given epitaxy a new place in IC fabrication. Selective SiGe epitaxial growth in the source-drain and extension regions of a pFET is already in production for 90 and 65 nm CMOS to provide strained Si channel. Ultimate CMOS of the future is envisioned to have non-Si channels including Ge and III-V compounds. Epitaxy, whether CVD based (RPCVD, UHCVD) or MBE, will play a central role for semiconductor material development. In this review we will describe relatively new applications of epitaxy for advanced hybrid oriented technology (HOT) viz SuperHOT, and a single wafers sSOI process by SIMOX.