Yanning Sun

Wafer-scale epitaxial graphene growth on the Si-face of hexagonal SiC (0001) for high frequency transistors

Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibiting room-temperature Hall mobilities up to 2750 cm2 V−1 s−1, measured from ungated, large, 160×200 μm2 Hall bars, and up to 4000 cm2 V−1 s−1, from top-gated, small, 1×1.5 μm2 Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using atomic force microscopy, high resolution transmission electron microscopy, and Raman spectroscopy. Furthermore, top-gated radio frequency field-effect transistors (rf-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si-face of SiC that exhibited Hall mobilities up to 1450 cm2 V−1 s−1 from ungated Hall bars and 1575 cm2 V−1 s−1 from top-gated ones. This is by far the highest cutoff frequency measured from any...

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

High-Performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}

FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vts are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious challenge due to poly-to-active overlay requirements and the need for raised S/D for series resistance reduction. A new FinFET design without S/D contact pads is thus proposed and a selective epitaxial process to merge individual fins is developed

-Channel MOSFETs With High-

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 μm down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron-hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac point in graphene devices as a consequence of gate length scaling. The unusual shift of the Dirac point voltage has been identified as one of the signatures of short-channel effects in GFETs.

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The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.

Gate Dielectrics and

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

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We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length LG = 30 nm. Our best short-channel devices exhibit peak saturation transconductance GMSAT = 1140 μS/μm at LG = 60 nm and supply voltage VDD = 0.5 V.

-Si Passivation

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.

Investigation of FinFET Devices for 32nm Technologies and Beyond

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.