van Ed Tuijl

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillators close-in phase noise. More specifically, it is shown that the 1/f/sup 3/ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f/sup 3/ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching.

A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects

Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-/spl mu/m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 /spl mu/m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.

A 3Gb/s/ch transceiver for RC-limited on-chip interconnects

A bus-transceiver chip in 0.13 /spl mu/m CMOS uses 10mm uninterrupted differential interconnects of 0.8 /spl mu/m pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects

A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work

A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.

AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier

This paper proposes the use of a variable-gain amplifier instead of a hard limiter for amplitude modulation (AM) suppression with low AM-PM (phase modulation) conversion. A hard limiter shows phase shift variations through input-amplitude dependent changes in output waveform, combined with bandwidth limitations. It is shown that these can be kept small only for limiter bandwidths much larger than the input frequency. A linear amplifier with variable gain used for AM suppression does not suffer from this problem. A CMOS variable-gain amplifier with gain-insensitive phase shift has been designed for this purpose. The benefits and limitations of the technique are explored with reference to an experimental 2.5 /spl mu/m BiCMOS chip for a television IF demodulator. Experimental and simulation results indicate that the AM-PM conversion can be kept below 0.5/spl deg/ at 40 MHz over an input amplitude range of 20 dB, where typical hard limiters show 3-5/spl deg/. This is achieved with an amplifier bandwidth of 80 MHz, while a hard limiter would need a bandwidth of more than 600 MHz to obtain similar results.

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.