Simon M. Louwsma

A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.

A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

A 1 Volt switched transconductor mixer in 0.18 /spl mu/m CMOS

A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 /spl mu/m CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit.

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2 and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.

Implementation of a High-speed Time-interleaved ADC

Chapter 4 describes the actual implementation of a high-speed time-interleaved ADC based on the design choices described in this book. Since timing calibration is hard to implement, a switch-driver circuit with low skew is introduced, such that timing calibration is not needed.

Sub-ADC Architectures for Time-interleaved ADCs

Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling time. A new overrange technique is presented called the single-sided overrange technique. Compared to a conventional SA-ADC, it saves 58% of the settling time, and therefore it can be more energy efficient.