Veronika Polei
Infineon Technologies
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Publication
Featured researches published by Veronika Polei.
MRS Proceedings | 2007
Torsten Mueller; Christoph Kleint; C. Fitz; M. Isler; S. Riedel; Jens-Uwe Sachse; Dominik Olligs; H. Boubekeur; F. Heinrichsdorf; Veronika Polei; David Pritchard; M. Verhoeven; L. Lattard; M. Markert; C. Schupke; B. Tippelt; S. Teichert; R. Reisdorf; C. Ludwig; E.G. Stein v. Kamienski; T. Mikolajick; Nicolas Nagel
A 63nm Twin Flash memory cell with a size of 0.0225μm 2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi 2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.
Archive | 2005
Lars Bach; Dominik Dr. Olligs; Torsten Mueller; Veronika Polei
Archive | 2002
Josef Willer; Veronika Polei
Archive | 2005
Thomas Mikolajick; Torsten Mueller; Nicolas Nagel; Lars Bach; Dominik Dr. Olligs; Veronika Polei
Archive | 2005
Laura Pescini; Achim Gratz; Veronika Polei
Archive | 2003
Veronika Polei; Josef Willer
Archive | 2005
Dominik Dr. Olligs; Torsten Mueller; Karl-Heinz Kuesters; Veronika Polei; Thomas Mikolajick; Josef Willer
Archive | 2002
Veronika Polei; Martin Welzel
Archive | 2006
Dominik Dr. Olligs; Veronika Polei
Archive | 2005
Achim Gratz; Mayk Roehrich; Veronika Polei