Victor Prokofiev

High-Speed Flex-Circuit Chip-to-Chip Interconnects

High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper construction of the flex ribbon is shown to improve the raw bandwidth over standard FR-4 boards by about three times. Active testing results from a 130-nm CMOS test vehicle show the potential of up to two times higher data rates. The next-generation test vehicle with 90-nm CMOS circuits gives improved voltage and timing margins at 20 Gb/s. In an interconnect limited case a channel with 36 in (91.4 cm) of flex runs at 18.2 Gb/s data rate at a bit-error ratio (BER) of better than 10-12. The channel includes two 90-nm CMOS test chips, two organic flip-chip package substrates, and two flex connectors; crosstalk is not included in this experiment. High-speed connector solutions, including results from a ldquosplit socketrdquo assembly test vehicle, are discussed in detail. The characterization of two top-side flex connector prototypes demonstrates their basic durability and good high-frequency performance. Samples survive 100 mating cycles at an average contact resistance of less than 30 mOmega, adequate for high-speed signaling. Measured differential insertion loss is less than 1.5 dB up to 10 GHz and less than 3.5 dB up to 20 GHz. Near-end and far-end crosstalk measurements indicate that the connectors exceed crosstalk specifications.

High frequency modeling and characterization of pin and land grid array sockets

A variety of CPU sockets are simulated and characterized for 2-port and &port S-parameters at high frequencies (45MhZ-15GHz) in single-ended and differential signaling configurations. Three-dimensional numerical simulations are performed with a commercially available FEM (f~te element method)-Based full-wave software: Ansoft HFSS. The simulation method, including three dimensional modeling, wave excitation and discretization, is rigorously validated with VNA (vector network analyzer) measurements. Using this developed simulation and measurement techniques, a PGA (pin grid array) socket with 478 pins and a LGA (land grid array) socket with 735 pins are analyzed and characterized to compare their performance for high-speed signaling applications. Both simulations and measurements are obtained with a test fmture consisting of motherboard transmission lines and socket adaptor vias, and their effects are removed using a de-embeddmg technique up to 15 GHz for 2-port as well as 4-port signaling. Validation results show very good correlation between numerical simulation and measurements for most critical electrical speciiications. The characterization results show that the LGA and PGA sockets have comparable performance to SGHz, but the PGA socket provides better frequency response from 8 to 15 GHz bandwidth for single ended and differential insertion and rem losses, referenced 50 ohms and 100 ohms respectively. Also, the differential frequency response (differential return and insertion losses) is better than that of single-ended signaling for these two sockets.

Package electrical specifications for giga bit signaling I/Os

Giga bit per second (Gb/s) signaling is rapidly proliferating in computing, networking and telecommunication systems. Giga bit signaling uses differential circuits for transmitter (TX) and receiver (RX) circuits. Often industry standards define system level performance metrics. Specifications for the majority of components, such as the package interconnect are not specified. At the Gh/s speeds. the package performance is a significant conttihutor to the system performance, and must he carefully specified to balance performance, cost, and manufacturing capability. The results of this work can he used to defme the package performance target using scattering (S) parameters in the frequency domain for design engineering. This specification can he used as a proxy for the package models in the overall cbannel between a pair of TX and RX. Then, the time domain analysis of the channel can provide system level performance metrics such as eye opening and jitter. This paper describes a methodology to specify the S parameters for a desirable level of performance in time domain. These specifications are normalized and scale with the speed of the input-output (VO) interface. Several examples are shown to show the trade off between the frequency domain performance and the impact on the time domain.

An accurate electromagnetic modeling of the die-to-die interconnect link for gigabit systems applications

The cost-effective design of gigabit per second signaling (Gb/s) for the interconnect systems requires optimizing components with accurate full channel simulations. The gigabit system performance is often defined in the time-domain (TD), but the modeling and characterization for the interconnect structures are done in the frequency-domain (FD). Due to non-linear behavior of the devices, the relation between FD and TD performances is not intuitively obvious, and therefore it is necessary to perform accurate analysis in both domains. To achieve an accurate modeling of the complex packaging structure often used a full-wave modeling tool that analyzes the propagation of electromagnetic waves through a three-dimensional model. In addition to the needs of characterization of the extended packaging boundaries, the accurate modeling utilizes a frequency-dependant material characterization. This paper describes the electromagnetic modeling methods, such as use of the frequency-dependent material properties, the method of discontinuity segmentation, and the validation technique. The vector network analyzer (VNA) where used for validation and choosing the best modeling method. Using measured and modeled data, we provide simulation in the time and the frequency domain, with comparison results. Good correlation between the modeling and measurement is reported in this paper.