Vijay Wakharkar

Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities

After decades of following the roadmap laid out by Moore’s law [1], silicon features have reached the nanoscale, which is below 100 nm in dimension, as illustrated in Fig. 22.1. The first logic products with 90-nm transistors, using the traditional silicon dioxide insulator and polysilicon gate, went into volume production in 2003. More recently in 2007, 45-nm devices using a revolutionary high-k metal gate transistor technology have been introduced [2, 3]. These nanoscale devices enable higher performance circuits, which in turn drive advanced features in their packaging. These devices can significantly lower the power consumption of high-performance logic products creating new applications in the fast-growing ultramobile market (Fig. 22.2) and thus requiring packaging to support the demands of these form factors. This chapter will discuss the challenges and opportunities in flip chip packaging for these nanoscale devices.

Future Direction and Challenges for Microelectronics Packaging Materials

The continual increasing performance of microelectronics products places a high demand on packaging technologies. This presentation will discuss the current environment, challenges, and technologies being pursued. Package technology migrations for microprocessors and communication products are described. Material needs for high thermal dissipation, high-speed signaling, and high-density interconnects are discussed. Microprocessor scaling for increased performance and reduced cost places significant challenges on power delivery and power removal due to reducing dimensions, operating voltages, and increasing power. Meeting these challenges indicates a need for advanced packaging solutions using advanced materials. New methodologies, metrologies, and materials/process technologies to address these challenges are also highlighted.Copyright