Vinayan C. Menon

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Overlay improvement roadmap: strategies for scanner control and product disposition for 5-nm overlay

To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally. Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be divided into 5 categories: scanner, process, reticle, metrology, and APC. In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay inside each field, rather than just at field corners. Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieving desired performance. In addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve the necessary overlay roadmap capability for current development efforts.

High-order wafer alignment in manufacturing

Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes. Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated. How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product specific corrections per exposure and 10 term APC process control.

Determining DOF requirements needed to meet technology process assumptions

Depth of Focus (DOF) and exposure latitude requirements have long been ambiguous. Techniques range from scaling values from previous generations to summing individual components from the scanner. Even more ambiguous is what critical dimension (CD) variation can be allowed to originate from dose and focus variation. In this paper we discuss a comprehensive approach to measuring focus variation that a process must be capable of handling. We also describe a detailed methodology to determine how much CD variation can come from dose and focus variation. This includes examples of the statistics used to combine individual components of CD, dose and focus variation.

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.