Vincent Wiaux

Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology

High-index-contrast, wavelength-scale structures are key to ultracompact integration of photonic integrated circuits. The fabrication of these nanophotonic structures in silicon-on-insulator using complementary metal-oxide-semiconductor processing techniques, including deep ultraviolet lithography, was studied. It is concluded that this technology is capable of commercially manufacturing nanophotonic integrated circuits. The possibilities of photonic wires and photonic-crystal waveguides for photonic integration are compared. It is shown that, with similar fabrication techniques, photonic wires perform at least an order of magnitude better than photonic-crystal waveguides with respect to propagation losses. Measurements indicate propagation losses as low as 0.24 dB/mm for photonic wires but 7.5 dB/mm for photonic-crystal waveguides.

Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography

We demonstrate single-mode photonic wires in silicon-on-insulator with propagation loss as low as 2.4 dB/cm, fabricated with deep ultraviolet lithography and dry etching. We have also made compact racetrack and ring resonators functioning as add-drop filters, attaining Q values larger than 3000 and low add-drop crosstalk.

Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

We present a number of compact wavelength-selective elements implemented in silicon-on-insulator (SOI) photonic wires. These include arrayed waveguide gratings (AWGs), Mach-Zehnder lattice filters (MZLFs), and ring resonators. The circuits were fabricated with deep UV lithography. We also address the sensitivity of photonic wires to phase noise by selectively broadening the waveguides, and demonstrate this in a compact AWG with -20 dB crosstalk and an insertion loss of 2.2 dB for the center channels

Basic structures for photonic integrated circuits in Silicon-on-insulator

For the compact integration of photonic circuits, wavelength-scale structures with a high index contrast are a key requirement. We developed a fabrication process for these nanophotonic structures in Silicon-on-insulator using CMOS processing techniques based on deep UV lithography. We have fabricated both photonic wires and photonic crystal waveguides and show that, with the same fabrication technique, photonic wires have much less propagation loss than photonic crystal waveguides. Measurements show losses of 0.24dB/mm for photonic wires, and 7.5dB/mm for photonic crystal waveguides. To tackle the coupling to fiber, we studied and fabricated vertical fiber couplers with coupling efficiencies of over 21%. In addition, we demonstrate integrated compact spot-size converters with a mode-to-mode coupling efficiency of over 70%.

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS® process is used, realizing narrow trenches with larger DOF and less LER. For mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is transferred successfully in the underlying low-k material.

Fabrication of photonic crystals in silicon-on-insulator using 248-nm deep UV lithography

We demonstrate wavelength-scale photonic nanostructures, including photonic crystals, fabricated in silicon-on-insulator using deep ultraviolet (UV) lithography. We discuss the mass-manufacturing capabilities of deep UV lithography compared to e-beam lithography. This is illustrated with experimental results. Finally, we present some of the issues that arise when trying to use established complementary metal-oxide-semiconductor processes for the fabrication of photonic integrated circuits.

Double patterning design split implementation and validation for the 32nm node

Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems conceived for the 65nm node to print 32nm node designs. In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions and present a new design rule for double patterning compliance checking applicable to full-chip scale.

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Ultralow-loss 3-dB photonic crystal waveguide splitter

A photonic crystal waveguide splitter that exhibits ultralow-loss 3-dB splitting for TE-polarized light is fabricated in silicon-on-insulator material by use of deep UV lithography. The high performance is achieved by use of a Y junction, which is designed to ensure single-mode operation, and low-loss 60 degrees bends. Zero-loss 3-dB output is experimentally obtained in the range 1560-1585 nm. Results from three-dimensional finite-difference time-domain modeling with no adjustable parameters are found to be in excellent agreement with the experimental results.

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.