Mireille Maenhoudt

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Using 193nm lithography at NA=0.75, the minimum pitch that can be obtained in a single exposure is 160nm for dark field structures that are used in single damascene interconnect processing. In order to evaluate the critical electrical parameters for the smaller technologies, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm. This corresponds to k1-factors of 0.27 to 0.19 for dense trenches. The designs have been split up into two layers at more relaxed pitch (twice the final pitch). The first step consists in patterning a small semi-isolated trench at this more relaxed pitch. Because of the limited resist resolution for semi-isolated trenches, shrink techniques such as resist reflow or RELACS are needed. After etching this first layer into a low-k material or metal hard mask, planarization of the topography is critical before performing the second exposure. The second exposure is then identical to the first one, but overlay to the first layer is extremely critical in order to get a reasonable process window. In this paper, we illustrate the feasibility of the double patterning technique for early sub-65nm-node evaluation of low-k materials. The resolution and processing limits will be shown for single layer resist processing with RELACS shrink for 193nm lithography at NA=0.75. The planarization for the second photo is done using organic BARC. We will also quantify the overlay requirements to measured and introduced overlay errors.

Novel aberration monitor for optical lithography

The aberration monitor allows independent determination of spherical, coma, astigmatism and three point in a single experiment using existing equipment. The monitor consists of a circular phase object, with a diameter of approximately (lambda) /NA and a phase depth of (lambda) /2. Due to the relative large diameter, the image prints as a narrow ring into the resist. Without aberrations its contours are concentric circles. Aberrations deform the ring in a characteristic way. A detailed analysis of the ring shape through focus identifies the aberrations of the projection lens. A linear aberration model is compared with simulations. Experimental results of various aberrations are shown and ar correlated to line width measurements and interferometric lens data.

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Alternative process schemes for double patterning that eliminate the intermediate etch step

Double patterning is used to scale designs below k1 factors that can be obtained with single patterning. Because of the double litho and etch steps, however, this is an expensive and time consuming technique. Spacer defined double patterning, which is commonly used to shrink regular dense patterns as used in memory applications, is an expensive technique because of the many deposition and etch steps that are required. In this paper, we propose several alternative process flows which can reduce the cost-of-ownership by eliminating the intermediate etch step in a double litho, double etch for line/space patterns, and replace it by a process step in the track only. These alternative process flows use thermal freezing resist, positive/negative resist and coating a freezing material. For these materials 32nm node logic patterning can be demonstrated, and even 32nm half pitch can be patterned already with one technique. As alternative technique to spacer defined double patterning, dual tone development is proposed, which can generate pitch doubling in resist using a single exposure. Proof-of-concept of this technique is shown experimentally.

Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations

Double patterning lithography (DPL)-either with two litho and two etches or through the use of a sacrificial spacer-are comparable in complexity and process control requirements. Since critical dimensions uniformity (CDU) and overlay requirements are considerably tighter than in single exposure, they present tougher challenges to process control, metrology, and integration, but seem feasible for 32-nm node. We study CDU and overlay requirements and performance at 32-nm-hp resolution for dual litho-etch and sacrificial spacer schemes. We bring in three particular aspects of CD control: the existence of multiple populations of lines and spaces, overlay entanglement into CDU performance, and the mechanism of doubled-pitch pattern generation from uncorrelated left and right edges, Accordingly, active compensation schemes are proposed to bring together these multiple CDU populations in order to achieve the typical 10% CD tolerance of the final pattern. Experimental results confirmed our assumptions of CDU-overlay entanglement and existence of multiple CD populations of lines and spaces. We present CDU results from before and after applying CD compensation schemes to improve CDU and overlay performance through active feed forward corrections. Results confirm the gain in improving statistical and spatial CD distribution to meet control levels required at 32-nm design rules: 2-nm CDU control per population, 3-nm CDU control for two adjacent lines, or spacer CD populations with 3-nm single machine overlay, all of them being demonstrated on multiple wafers and immersion scanners.

Double patterning for 32nm and below: an update

Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to process control, metrology and integration, but seem feasible for the 32nm node. In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple populations in order to meet comparable 10% CDU as in single exposure. We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU populations entangled overlay into CDU.

Ultimate contact hole resolution using immersion lithography with line/space imaging

Contact Hole (CH) resolution is limited by the low aerial image contrast using dark field masks. Moreover the 2- Dimensional character of CH is a limiting factor in the use of extreme Resolution Enhancement Techniques for reaching the smallest pitch. These limitations can be overcome if one deconvolves the 2D CH into two exposures of 1D structures (i.e. lines). These 1D structures can indeed be printed at the ultimate resolution limit of the scanner using dipole exposures. Recently, several materials have become available to pattern CH from such a double exposure of line patterns. It is shown in this paper how this concept of deconvolution can be used in different techniques: Two 1D aerial images can be recomposed in order to obtain 2D images which will subsequently be reversed into CH. We can distinguish, on the one hand, a reversal based on the positive development of line crossings into resist pillar patterns, on which are deposited or coated a gap-fill material layer. The pillars are then removed, leaving a masking material layer with holes. On the other hand, negative tone development can be used to reverse directly the recomposed 2D aerial image: while the classical positive development creates pillars, the negative tone development inverses immediately this image to create contact holes in the resist layer. In this paper, we demonstrate the potential of the double exposure method. We characterise three reversal techniques using a NA=1.35 immersion scanner for patterning 40nm or lower CH at pitch 80nm. We also show etch performance of these processes and address the complexity of each solution.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.