Staf Verhaegen

Double patterning design split implementation and validation for the 32nm node

Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems conceived for the 65nm node to print 32nm node designs. In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions and present a new design rule for double patterning compliance checking applicable to full-chip scale.

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Interactions of double patterning technology with wafer processing, OPC and design flows

Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Model-based OPC for first-generation 193-nm lithography

The first 193 nm lithography processes using model-based OPC will soon be in production for 0.13 micrometer technology semiconductor manufacturing. However, the relative immaturity of 193 nm resist, etch and reticle processes places considerable strain upon the OPC software to compensate increased non-linearity, proximity bias, corner rounding and line-end pullback. We have evaluated three leading model-based OPC software packages with 193 nm lithography on random logic poly gate designs for the 0.13 micrometer generation. Our analysis has been performed for three different OPC reticle write processes, two leading 193 nm resists and multiple illumination conditions. The results indicate that the maturity of the model-OPC software tools for 193 nm lithography is generally good, although specific improvements are recommended.

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography. Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results. Recently, freeform illumination has become available through pixelated DOEs or through FlexRayTM, ASMLs programmable illuminator system, allowing for virtually unconstrained intensity distribution within the source pupil. In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization (SMO) for an aggressive use case, and wafer-based verification. For a 22 nm node SRAM of 0.099 μm² and 0.078 μm2 bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of SMO and freeform illumination. In this work, both pixelated DOEs and FlexRay are applied. Additionally, the match between the latter two is confirmed on wafer, in terms of CD and process window.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Assessment of OPC effectiveness using two-dimensional metrics

A complete evaluation of the optical proximity effects (OPE) and of their corrections (OPC) requires a quantitative description of two-dimensional (2D) parameters, both at resist- and at reticle-level. Because the 2D behaviour at line-ends and at line-corners can become a limiting factor for the yield, it should be taken into account when characterising a process, just as the CD- and pitch-linearity are already kept under control. This implies the measurement of 2D-metrics in a precise way. We used an SEM Image Analysis tool (ProDATA SIAM) to define and measure various OPC-relevant metrics for a C013 process. For the METAL (M1) process, we show that the overlap between line-ends of M1-trenches and underlying nominal contacts is a relevant metric to describe the effectiveness of hammerheads. Moreover, it is an interesting metric to combine with the CD process window. For the GATE process, we demonstrate that for a given set of metrics there is a degree of OPC aggressiveness beyond which it is not worth to go. We considered both line-end shortening (LES) and corner rounding affecting the poly linewidth close to a contact pad, and this on various logic circuits having received different degrees of fragmentation. Finally the knowledge of the actual line-end contour on the reticle allows one to simulate separately the printing effect of that area loss at reticle line-ends. The area loss measured by comparing the extracted contour to the target one is regarded as a combination of pull-back and area loss at corners. For our C013 gate process, and for the 130nm lines at a 1:1.25 duty cycle, those two parameters contribute together to approximetely 40% of the measured LES in the resist. This fact raises the question of specifications on 2D reticle parameters. We also find a linear correlation between the area loss at reticle line-end corners and the corresponding increase of LES on the wafer, which suggests a way towards putting specifications on the reticle line-ends.

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Today, 22nm node devices are built using 193nm immersion lithography, possibly combined with double patterning techniques. Some stretch till the 16nm node is feasible here, using double, triple or even quadruple patterning. Alternatively, extreme ultra violet (EUV) lithography is showing promising results, and is considered to be the most likely option for this last mentioned device node. Electrically functional 22nm node devices are already available, where EUV lithography is used for the definition of the back-end layers. Fewer results are published on the patterning of front-end layers using EUV lithography. In this work, EUV lithography is used for the patterning development of the first four critical layers (active or fin, gate, contact and metal1) of a 16nm node 6T-SRAM cell. For the first time, front-end layers will need to be printed, with EUV, and transferred into an underlying substrate. The need for optical proximity correction is checked and characterized for all layers.