Vito Boccuzzi

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

A CMOS GSM IF-sampling circuit with reduced in-channel aliasing

A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-/spl mu/m CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.

Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors

A new differential tuning concept for LC oscillator is introduced and demonstrated on a 4.5GHz CMOS VCO. It uses inductive coupling of varactors, giving highly linear differential tuning with good common-mode rejection. Only one type of varactor is used, allowing the designer to use the varactor-type with the highest C/sub max//C/sub min/ ratio and/or quality factor. It is shown that differential tuning offers a means to suppress the upconversion of common-mode bias noise, allowing for a significant power reduction in the VCOs bias circuitry. The realized VCO combines differential tuning constant K/sub VCO/ is 65MHz/V. The measured phase noise is lower than -124dBc/Hz at 1 MHz offset over the entire tuning range. The circuit, including bias, draws 5.5mA from a 2.5V supply.

A power efficient channel selection filter/coarse AGC with no range switching transients

This paper presents a channel selection filter/coarse AGC system implemented in a 0.25 /spl mu/m digital CMOS process. The system uses multiple filtering paths, each optimized for part of the required total dynamic range, resulting in small power dissipation (9 mA at 2.5 V) and chip area (0.7 mm/sup 2/). The individual filtering paths operate continuously, providing undisturbed output over the entire time, contrary to conventional AGC-filter schemes. The fabricated prototype maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB, over a 48 dB signal range, with good blocker immunity.

A CMOS IF sampling circuit with reduced aliasing for wireless applications

An IF-sampling technique rejects even-order alias channels. A 0.25 /spl mu/m CMOS test chip demonstrates 27 dB anti-aliasing rejection, 70 dB dynamic range, and -121 dBm/Hz noise floor, for a 377 MHz IF GSM signal, with 52 MHz sampling rate.

7V tristate-capable output buffer implemented in standard 2.5 V CMOS process

This paper describes high-voltage CMOS buffer architecture that uses low-voltage transistors. The voltage capability of the presented architecture is nearly three times larger than the voltage capability of the used MOSFETs. This buffer topology could be used to provide 3.3 V compatibility of 1.2 V and 1.5 V digital ICs implemented in standard CMOS technology. A 7 V circuit-prototype was fabricated in 0.25 /spl mu/m 2.5 V CMOS technology. Performed measurements demonstrate stress-free operation in both active and high-impedance mode.

A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver

A PLL-technique is introduced to enable fast switching of an 802.11 transceiver local oscillator (LO) between a low-and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CP) and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filter charge. A 50 kHz bandwidth integer-N PLL achieves a measured 7 MHz-jump with /spl plusmn/20 kHz accuracy within 60 /spl mu/s. The measured phase noise is -123 dBc/Hz at 1 MHz offset.