Vito Rutigliani

Vacuum ultra-violet damage and damage mitigation for plasma processing of highly porous organosilicate glass dielectrics

Porous organosilicate glass thin films, with k-value 2.0, were exposed to 147 nm vacuum ultra-violet (VUV) photons emitted in a Xenon capacitive coupled plasma discharge. Strong methyl bond depletion was observed, concomitant with a significant increase of the bulk dielectric constant. This indicates that, besides reactive radical diffusion, photons emitted during plasma processing do impede dielectric properties and therefore need to be tackled appropriately during patterning and integration. The detrimental effect of VUV irradiation can be partly suppressed by stuffing the low-k porous matrix with proper sacrificial polymers showing high VUV absorption together with good thermal and VUV stability. In addition, the choice of an appropriate hard-mask, showing high VUV absorption, can minimize VUV damage. Particular processing conditions allow to minimize the fluence of photons to the substrate and lead to negligible VUV damage. For patterned structures, in order to reduce VUV damage in the bulk and on feature sidewalls, the combination of both pore stuffing/material densification and absorbing hard-mask is recommended, and/or the use of low VUV-emitting plasma discharge.

Setting up a proper power spectral density (PSD) and autocorrelation analysis for material and process characterization

Power spectral density (PSD) analysis is playing more and more a critical role in the understanding of line-edge roughness (LER) and linewidth roughness (LWR) in a variety of applications across the industry. It is an essential step to get an unbiased LWR estimate, as well as an extremely useful tool for process and material characterization. However, PSD estimate can be affected by both random to systematic artifacts caused by image acquisition and measurement settings, which could irremediably alter its information content. In this paper, we report on the impact of various setting parameters (smoothing image processing filters, pixel size, and SEM noise levels) on the PSD estimate. We discuss also the use of PSD analysis tool in a variety of cases. Looking beyond the basic roughness estimate, we use PSD and autocorrelation analysis to characterize resist blur[1], as well as low and high frequency roughness contents and we apply this technique to guide the EUV material stack selection. Our results clearly indicate that, if properly used, PSD methodology is a very sensitive tool to investigate material and process variations

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

EUV photoresist patterning characterization for imec N7/N5 technology

In the last year, the continuous efforts on the development of extreme ultraviolet (EUV) lithography has allowed to push the lithographic performance of the EUV photoresists on the ASML NXE:3300 full field exposure tool. Today imec N7 node (equivalent to foundry N5) is the first scaling node at which industry will likely insert EUV into production which will bring a reduction in processing steps therefore reducing total cost of ownership [1], increasing yield and reducing time to ramp. However, the high-volume-manufacturing (HVM) requirement to have a cost-effective low exposure dose photoresist (<20mJ/cm2) remains a big challenge and roughness and pattern defectivity at nano-scale are the major limiting factors of the lithographic process window of EUV resist when looking at tight pitches below 40nm [2, 3]. To be effective during the lithographic EUV material screening phase for such tight pitches, it is necessary to implement complementary metrology analyses that can provide precise information on the resist roughness and a quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, the random nature of the light-matter interaction and consequent chemical reactions. Beside the traditional approach to characterize a resist with metrics as exposure latitude (EL%), depth of focus (DoF) and line-edge-roughness (LER) based on CDSEM measurements, we have used the power spectra density (PSD) [4] to get an unbiased value of the resist line roughness (LWR and LER) by using Fractilia metroLERTM commercial software. Further, we have used Stochalis imec software [5] to quantify patterning nano failures providing an early stage assessment on the patterning fidelity of the examined resists. We present the resist characterization results for 32nm dense line-space pattern on different substrates and for 36nm dense and orthogonal contact hole pitch pattern for different photoresists. Two positive tone chemically amplified (CA) resists have been identified at the exposure dose of 45mJ/cm2 and 33mJ/cm2 for logic (pitch 32nm dense line/space) and memory (pitch 36nm dense contact holes) use cases, respectively.

Optimized pore stuffing for enhanced compatibility with interconnect integration flow

Plasma processing of porous órgano-silicate Iowie dielectrics, following the damascene approach. remains one the biggest challenge for IC manufacturing. During low-k plasma etching. reactive radicals (O*, F* amongst others) and VUV penetrate easily into the porous low-k structure, reacting with Si-CH3 terminating bonds, ultimately turning the etched low-k hydrophilic and raising the integrated k-value beyond acceptable limits.

Multifractal analysis of line-edge roughness

In this paper, we propose to rethink the issue of LER characterization on the basis of the fundamental concept of symmetries. In LER one can apply two kinds of symmetries: a) the translation symmetry characterized by periodicity and b) the scaling symmetry quantified by the fractal dimension. Up to now, a lot of work has been done on the first symmetry since the Power Spectral Density (PSD), which has been extensively studied recently, is a decomposition of LER signal into periodic edges and quantification of the ‘power’ of each periodicity at the real LER. The aim of this paper is to focus on the second symmetry of scaling invariance. Similarly to PSD, we introduce the multifractal approach in LER analysis which generalizes the scaling analysis of standard (mono)fractal theory and decomposes LER into fractal edges characterized by specific fractal dimensions. The main benefit of multifractal analysis is that it enables the characterization of the multi-scaling contributions of different mechanisms involved in LER formation. In the first part of our work, we present concisely the multifractal theory of line edges and utilize the Box Counting method for its implementation and the extraction of the multifractal spectrum. Special emphasis is given on the explanation of the physical meaning of the obtained multifractal spectrum whose asymmetry quantifies the degree of multifractality. In addition, we propose the distinction between peak-based and valley-based multifractality according to whether the asymmetry of the multifractal spectrum is coming from the sharp line material peaks to space regions or from the cavities of line materis (edge valleys). In the second part, we study systematically the evolution of LER multifractal spectrum during the first successive steps of a multiple (quadruple) patterning lithography technique and find an interesting transition from a peak-based multifractal behavior in the first litho resist LER to a valley-based multifractality caused mainly by the effects of etch pattern transfer steps.

Ultimate edge-placement control using combined etch and lithography patterning optimizations

Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho cooptimization to less than 1.0nm 3σ. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.

Computational nanometrology of line-edge roughness: noise effects, cross-line correlations and the role of etch transfer

The aim of this paper is to investigate the role of etch transfer in two challenges of LER metrology raised by recent evolutions in lithography: the effects of SEM noise and the cross-line and edge correlations. The first comes from the ongoing scaling down of linewidths, which dictates SEM imaging with less scanning frames to reduce specimen damage and hence with more noise. During the last decade, it has been shown that image noise can be an important budget of the measured LER while systematically affects and alter the PSD curve of LER at high frequencies. A recent method for unbiased LER measurement is based on the systematic Fourier or correlation analysis to decompose the effects of noise from true LER (Fourier-Correlation filtering method). The success of the method depends on the PSD and HHCF curve. Previous experimental and model works have revealed that etch transfer affects the PSD of LER reducing its high frequency values. In this work, we estimate the noise contribution to the biased LER through PSD flat floor at high frequencies and relate it with the differences between the PSDs of lithography and etched LER. Based on this comparison, we propose an improvement of the PSD/HHCF-based method for noise-free LER measurement to include the missed high frequency real LER. The second issue is related with the increased density of lithographic patterns and the special characteristics of DSA and MP lithography patterns exhibits. In a previous work, we presented an enlarged LER characterization methodology for such patterns, which includes updated versions of the old metrics along with new metrics defined and developed to capture cross-edge and cross-line correlations. The fundamental concept has been the Line Center Roughness (LCR), the edge c-factor and the line c-factor correlation function and length quantifying the line fluctuations and the extent of cross-edge and cross-line correlations. In this work, we focus on the role of etch steps on cross-edge and line correlation metrics in SAQP data. We find that the spacer etch steps reduce edge correlations while etch steps with pattern transfer increase these. Furthermore, the density doubling and quadrupling increase edge correlations as well as cross-line correlations.

Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist

In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.