Von Kamienski Elard Dr. Stein

Bitline contacts in a memory cell array

Non-volatile nor semiconductor memory device and method for the programming thereof

Integrated logic circuit

Native field effect transistor and method of manufacturing same

USB interface plug in electronic unit has moulded housing with electronic components including multiple layer connections through lead frame integrated in connector

Verfahren zur Herstellung von Charge-trapping-Speicherbauelementen A process for the preparation of charge-trapping memory devices

Contacts de ligne binaire dans une matrice de cellules memoire

Halbleiteranordnung und Verfahren zu ihrer Herstellung A semiconductor device and process for their preparation

Production of trenched bit lines in a semiconductor memory comprises using a mask which is produced whilst an auxiliary layer is applied on the whole surface and structured using a lacquer mask

Wafer testing and marking process for semiconductor components with fusing structures