Patrick Haibach

Validation of 30 nm process simulation using 3D TCAD for FinFET devices

This paper targets to show feasibility of a three-dimensional process simulation flow in the context of optimization of the device design and the underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm FinFET devices. The major goal of the simulation work is to implement a complete FinFET process flow into a commercially available 3D process simulation environment. Furthermore, all important three-dimensional geometrical features, such as corner roundings and 3D facets, have been introduced into the simulation set-up. After the successful demonstration of a functional 3D process simulation flow, detailed issues of process simulation methodology are assessed, such as the usage of different dopant diffusion models or the modelling of specific oxidation processes plus assessment of different annealing conditions. Finally, a comparison of the simulation results with electrical measurement data is performed which shows fairly good agreement.

Optimization of Halo Implant Using 3D TCAD for Nanoscale MuGFETs

This work presents a theoretical design analysis of halo implants for n-MuGFETs using commercial three-dimensional (3D) TCAD simulation tool. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices. Process and device simulations of halo implants have been performed with different nitride spacer, fin thicknesses and gate lengths. We see that thick nitride spacers (50 nm) and thinner fins (30 nm) are beneficial for 80 nm doped channel n-MuGFETs. Similarly, the role of halo implant is critical to suppress the short channel effects for small gate lengths (65, 50 nm etc) devices. Although, the halo implant is beneficial to adjust the threshold voltage to a required value, its presence is counter productive from the point of view of degradation in ION particularly for long channel devices. Using pre-development process results of our MuGFETs, good agreement was obtained with simulations and experimental data in terms of threshold voltage roll-off, ION/IOFF and short channel effects

On the assessment of various implants using 3D TCAD for FinFETs

This work deals with the junction and channel optimization on FinFET devices. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices at Infineon. Similar to real devices, important 3D geometrical features, such as corner roundings and 3D facets have been introduced into the simulation setup, which is based on commercially available 3D process simulation software (Taurus 3D). The influence of various unit process steps, such as channel implant, and LDD implant on the electrical performance of the devices have been evaluated. Beside the successful demonstration of a functional 3D process simulation flow, detailed issues of process and device simulation methodology such as the usage of different dopant diffusion and mobility models are assessed. Finally, a comparison of the simulation results with electrical measurement data is performed which fairly shows excellent agreement.