Wanlan Yang

An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.

Design of Ultra-Low Phase Noise and High Power Integrated Oscillator in

A novel ultra-low phase noise and high power integrated oscillator is presented in this letter. The proposed oscillator, based on GaN-on-SiC high electron mobility transistor (HEMT) with 0.25 μm gate length and 800 μm gate width, delivers 21 dBm output power when biased at VGS=-3 V and VDD = 28 V. Phase noise was measured to be -112 dBc/Hz at 100 kHz offset and -135 dBc/Hz at 1 MHz offset from 7.9 GHz carrier, respectively. To the best of our knowledge, it achieves the lowest phase noise compared to other GaN HEMT based integrated oscillators. It is also comparable in performance to the state-of-the-art ultra-low phase noise oscillators designed in InGaP technology, while delivering more than 10 times higher output power. In addition, this oscillator also exhibits a minimum second harmonic suppression of 28.65 dBc and more than 60 dBc third harmonic suppression. The chip size is 1.1×0.6 mm2. The results show that the proposed oscillator has the potential to be used for both low phase noise and high power microwave source applications.

0.25~\mu{\rm m}

In this letter, a compact and high-performance patch antenna array is developed for 60-GHz applications. The method to enhance both the gain and the frequency bandwidth of the antenna array simultaneously by using a parallel-series feed network together with the differential feeding technique is studied thoroughly. The tested antenna array achieves operation bandwidth ( ) from 55 to 68 GHz, which covers worldwide 60-GHz unlicensed band of 57-66 GHz, with peak gain of 12.8-15.6 dBi. The measured -3-dB beamwidths at 61.5 GHz are around ±13° in E-plane and ±15° in H-plane, respectively. The designed high-gain antenna array has a compact size of only 20 ×14 mm2 excluding the connector footprint for test.

GaN-on-SiC HEMT Technology

A 6-bit programmable gain amplifier (PGA) with current mode exponential gain control is presented in this paper that achieves a linearity error within ±0.1 dB over a 30-dB wide gain control range. The proposed design topology has two digitally-variable gain amplifiers and a post amplifier that are interconnected by a differential pair wideband matching network to provide an enhanced gain bandwidth product. The proposed PGA has 35 mW power consumption and occupies 0.25 mm2 core die area.

A Compact High-Performance Patch Antenna Array for 60-GHz Applications

This paper presents a 10-μA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature. Based on the proposed structure, a 130 ppm/°C temperature coefficient current reference across -40°C to 80°C temperature range is achieved. The proposed circuit can work at supply voltage varying from 2.4 to 3.0 V, while only has 30-nA drift at room temperature. The proposed current reference is implemented in 0.18-μm CMOS process occupying an area of 0.005 mm2.

A 35 mW 30 dB gain control range current mode programmable gain amplifier with DC offset cancellation

This paper presents the design of a programmable gain amplifier (PGA) that serves as an interface between the receiver front-end and the baseband processor. The proposed PGA design is fabricated in a commercial 0.18- μm SiGe BiCMOS process with a topology consisting of two digitally variable gain amplifiers cascaded by a post amplifier and interconnected by differential wideband matching networks that presents an overall enhanced gain bandwidth product. By using the current mode exponential gain control technique, the proposed design achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than -10 dBm, input/output return loss better than 13 dB, a ±0.75-dB gain flatness over a multi-decade frequency range from 2.5 MHz to 1.17 GHz, a measured in-band group-delay variation of 30 ps, a 35-mW power consumption, and a 0.25- mm2 core die area.

A low TC, supply independent and process compensated current reference

This paper presents a compact and efficient 60-GHz on chip antenna that may be realized with the back-end-of-line process of standard CMOS silicon Technology on low resistivity 10 Ω.cm silicon substrate. A planar tab monopole antenna structure is adopted and the feeding network is designed with 50Ω substrate-shielded CPW line. The designed antenna has a compact size of 1.5mm*1.0mm, including feed line and pads which are the integral parts of the antenna. Ansoft HFSS is used for design simulation with results centered at 60 GHz as following: the maximum gain is around 0.1dBi, the radiation efficiency is around 39%, the VSWR is less than 1.5 from 51.5 GHz to 70.6 GHz and the minimum return loss is around -36dB to achieve a better quality of impedance matching. The designed on-chip antenna can be used for the integration of a 60 GHz single-chip transceiver.

A 35-mW 30-dB Gain Control Range Current Mode Linear-in-Decibel Programmable Gain Amplifier With Bandwidth Enhancement

This paper presents the design of a low profile dual-band (on- / off-body modes) planar antenna in meandered shape with microstrip line feed for biomedical applications. The antenna is designed to operate in the ZigBee dual band 868-928 MHz and 2.4-2.5 GHz respectively. While the proposed antenna is simulated on direct surface of human skin model, it shows a good performance with the broad bandwidth for |S11| less than -10 dB. The antenna is designed with 50 Ω input port and on LTCC substrate (εr = 7.1, tanδ = 0.005) with miniaturized volume of 16.5 mm × 17 mm × 0.8 mm.

A 60GHz on-chip antenna in standard CMOS silicon Technology

In this paper, a low insertion loss, high isolation, ultra wideband (DC to 50 GHz) single-pole double-throw (SPDT) switch using 0.13 μm SOI technology is presented. The switch is designed by using a series-shunt configuration with input and output matching networks. The channel length and gate bias impacts on switch performance are studied. It is found that the transistor channel length has dominant effects on both the insertion loss and isolation. The measured insertion loss of the SPDT with 0.13 μm channel length transistor is less than 1.9 dB up to 50 GHz, while the isolation is better than 27 dB. Measured P1dB for SPDT switch is larger than 12 dBm. The active chip area of designed SPDT switch is only 0.21 × 0.19 mm2.

A compact dual-band meander-line antenna for biomedical applications

This paper presents a design process and simulation results of a U-shaped antenna over an artificial magnetic conductor (AMC) using a standard 65-nm CMOS technology for 60-GHz applications. The structure of the proposed on-chip antenna consists of a U-shaped monopole antenna fed with conductor-backed CPW line at the terminal aluminum layer LB and a novel AMC constructed with M1 to M6 metal layers. Ansoft HFSS is used for design simulation. Based on the simulated results after optimization, the U-shaped CPW-fed monopole antenna mounted on the AMC can offer higher gain and wider impedance bandwidth while maintaining an electrical size reduction.