Wayne I. Kinney

Signal magnitudes in high density ferroelectric memories

Abstract We review several issues affecting the signal delivered to a sense-amp in high density ferroelectric nonvolatile memories. Typical DRAM parameters are used to approximate the expected signal and to determine constraints on ferroelectric properties. These calculations pertain to memories which are destructively read and which use either a 1T/1C (one cell per bit) or a 2T/2C (two cells per bit) architecture.

An Update on Emerging Memory: Progress to 2Xnm

This paper will give an update on the status of emerging memory (EM) and potential markets. The more popular EM technologies will be reviewed, including PCM, RRAM, and STRAM. The biggest challenges for each technology will be highlighted.

Effects of Source Diffusion on SILC and Cycling-Induced Charge Loss in Source-Bias Erase Flash Cells

A recent report reveals that in source-bias erase flash cells, light source doping can cause room temperature erratic charge loss after program/erase cycling. In this paper, we present tunnel oxide hole trapping and stress induced leakage current (SILC) measurements under source-bias erase stress conditions, in cell structures with different source doping profiles. Data suggests the deep depletion in cell source during erase causes hole trapping in tunnel oxide above the source diffusion, which is responsible for the room temperature charge loss after P/E cycling for light doping source