Marc Demand

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS performance is demonstrated for narrow fins and short gates. Further improvement in nMOS performance can be achieved by eliminating access resistance that is currently attributed to poor re-crystallization of implantation damage in narrow fins. Fully-depleted FinFETs show strongly improved short channel effect (SCE) control when the fin width is scaled, even without halo-implants. Nearly ideal DIBL and sub-threshold slope (SS) are achieved down to 30nm gate length. Low leakage devices are realized by combining a fully depleted channel, HfSiO high-k dielectric, mid-gap TiN metal electrodes, and aggressive fin width scaling. Symmetrical threshold voltages (±0.35 V) are achieved. It is demonstrated that selective epitaxial growth on source and drain regions is essential to limit parasitic resistance in narrow fin devices. Parametric spread is dominated by gate length variations in short devices but within-die fin width variations are still evident for long devices.

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

We demonstrate for the first time the performance of aggressively scaled triple gate devices with a MOCVD TiN/HfO gate stack. The transistors have physical gate lengths down to 40 nm, and 60 nm tall and 10 nm wide fins. We show that MOCVD TiN can be used to successfully set the threshold voltage of both nMOS and pMOS devices in the range of |0.4-0.5| V. Devices with excellent Ion/Ioff behavior were obtained with reduced gate leakage values.

A new complementary hetero-junction vertical Tunnel-FET integration scheme

This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby a sacrificial source layer is used during the device fabrication and replaced by the final hetero-source materials, respectively for n- or p-TFETs, thereby minimizing the thermal budget applied to the source junctions. With the demonstration of this source-replacement-last module for a vertical Ge hetero-junction n-TFET, we show that it is possible to grow highly doped hetero-junctions on a Si channel with steep doping profiles and without damaging the high-κ gate-dielectric interface. This scheme allows for the integration of complementary low-bandgap materials on a Si platform providing high on-currents combined with the Si channel based low off-currents.

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

Gatestacks for scalable high-performance FinFETs

Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby a dummy source is replaced at the end of the process flow by the final source material to form an heterojunction. We show that the source can be successfully replaced while maintaining the gate dielectric integrity in the gate-source overlap (GS-OL) region and selectively to the exposed materials. Due to the in situ-doped epitaxial-grown source and the low thermal budget, this integration scheme leads to the formation of a highly doped source and an abrupt tunnel heterojunction and allows the integration of complementary devices. Electrical characterization of the devices shows performance improvement over their SiGe-source heterojunction and Si homojunction vertical TFET counterparts. Temperature dependence indicates that the subthreshold region of the devices is degraded due to trap-assisted tunneling (TAT). Band-to-band tunneling (BTBT) contribution is, however, revealed at low temperature (78 K) with a minimum point slope of ~50 mV/decade. The impact on performance of different device parameters is assessed. The amount of GS-OL or crystalline Ge (c-Ge) thickness in the source does not affect the device characteristics owing to the fact that the devices are dominated by point tunneling. On the other hand, the thickness of the gate dielectric as well as the doping profile at the tunnel junction modifies the device performance. The gate-drain underlap is shown to reduce the ambipolar behavior of the devices without affecting their ON-characteristics. Very low variability is measured for the ON-current in the devices where BTBT dominates, while variability increases in the TAT region.

Silicon Nano-Pillar Test Structures for Quantitative Evaluation of Wafer Drying Induced Pattern Collapse

Silicon nano-pillars as test structures for quantitative evaluation of advanced wafer drying are presented. The method consists of the use of pillar structures with an aspect ratio up to 28 in combination with top-down SEM inspection and subsequent image analysis for quantification. The test vehicle allows characterizing cleaning techniques by a threshold aspect ratio below which value the features do not collapse. As such, a higher critical aspect ratio corresponds to a superior wetting/drying method. Furthermore, as the metrology is specific and includes cluster size distribution analysis, it can bring new insights in the mechanism of pattern collapse.

High yield sub-0.1µm 2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Low V t Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

This paper reports a novel approach to implement low V_t Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET V_t by 300 mV/500 mV on HfSiON/SiON (resulting in a V_t,lin of 0.25 V/0.18 V respectively), w/o compromising the T_inv (<1 Aring variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150times lower J_g wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low V_t CMOS using either dual phase (NiSi, Ni₃₂Si₁₂) or single phase (Ni₂Si) FUSI gate for both n-and pFETs.