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Featured researches published by Willy Hioe.


IEEE Transactions on Applied Superconductivity | 1991

Quantum flux parametron: a single quantum flux device for Josephson supercomputer

Mutsumi Hosoya; Willy Hioe; Juan Casas; Ryotaro Kamikawai; Yutaka Harada; Yasou Wada; Hideaki Nakane; Reiji Suda; Eiichi Goto

A quantum flux parametron (QFP), a single quantum flux superconductive device that has a potential of up to 100-GHz switching with nW-order power dissipation, is considered. The potential of the QFP and key technologies when QFPs are applied to a Josephson supercomputer are described. Switching speed, stability, and power dissipation of a QFP are discussed. QFP gates, circuits, and systems are next described. Then, ultra-fast clock distribution using a standing wave is explained. High-speed operation at more than 10 GHz and 10/sup 14/ error-free operations per QFP have been demonstrated. Finally described is a high-density packaging scheme by three-dimensional integration, which is very important for ultra-high speed circuits because the propagation delay becomes dominant in such circuits.<<ETX>>


ieee gallium arsenide integrated circuit symposium | 1997

A 77 GHz T/R MMIC chip set for automotive radar systems

Keigo Kamozaki; Naoyuki Kurita; Willy Hioe; Takuma Tanimoto; Hiroshi Ohta; Toru Nakamura; Hiroshi Kondoh

A 77-GHz MMIC chip set consisting of a low noise amplifier, a power amplifier, a down converter and a voltage controlled oscillator has been developed to constitute a T/R module for automotive radar systems. The low noise amplifier exhibited a gain of 9.5 dB/spl plusmn/1.0 dB over a 62-96.5 GHz band with an NF of 5.8 dB. The power amplifier achieved a small-signal gain of 13.5 dB/spl plusmn/2.5 dB from 70.7 GHz to 80.3 GHz with 9.7 dBm output power at the 1 dB gain compression. The down converter exhibited a conversion gain of 1.3 dB/spl plusmn/2.2 dB in a band between 75 GHz and 98 GHz with an NF of 7.5 dB. The 77-GHz voltage controlled oscillator exhibited an output power of 0.9 dBm/spl plusmn/0.9 dB over a tuning range of 75.5-76.6 GHz. A design philosophy has been adopted of achieving broadband performance in small MMIC chip size in order to improve manufacturability and performance/cost characteristics of the chip set. The total area for the chip set is 7.92 mm/sup 2/.


IEEE Journal of Solid-state Circuits | 2004

Novel automatic tuning method of RC filters using a digital-DLL technique

Takashi Oshima; Kenji Maio; Willy Hioe; Yoshiyuki Shibahara

A novel automatic tuning method for RC filters is proposed for CMOS low-IF transceivers. The method is based on a digital-DLL-like technique and tunes the time constant of filters automatically. The tuning range and the tuning accuracy are analyzed theoretically. To verify the method, a sixth-order 2-MHz IF filter for Bluetooth and a tuning circuit were fabricated in 0.18-/spl mu/m CMOS. The tuning circuit occupying 0.066 mm/sup 2/ includes only a reference first-order filter, a comparator, and a simple digital circuit. The measurement result of the filter and the tuning circuit shows that the maximum /spl plusmn/28% time-constant variation can be tuned within /spl plusmn/5% accuracy, which is consistent with theoretical results.


IEEE Transactions on Applied Superconductivity | 1995

Superconducting packet switch

Mutsumi Hosoya; Toshikazu Nishino; Willy Hioe; Shinya Kominami; Kazumasa Takagi

Very broad band throughputs greater than 1T bit/sec are desired in heavily loaded communication systems. Using the merits of superconducting devices, a superconducting network system is expected to improve the throughputs of such communication bottleneck systems. The paper describes a superconducting packet switch which is indispensable to a proposed superconducting network system. Considering the characteristics of various switch architectures, the space-division Banyan type architecture is adopted for a superconducting packet switch proto-type. The complete design of the proto-type is performed and the total operation is numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is a key component of the proto-type. The basic switching element with one-bit data width is fabricated and the correct operation is completely confirmed.<<ETX>>


custom integrated circuits conference | 2003

Automatic tuning of RC filters and fast automatic gain control for CMOS low-IF transceiver

Takashi Oshima; Kenji Maio; Willy Hioe; Yoshiyuki Shibahara; Takeshi Doi

Automatic tuning of RC filters and fast automatic gain control (AGC) of cascaded programmable amplifiers were proposed and verified by a 0.18 /spl mu/m CMOS prototype IC. The tuning circuit includes a dummy 1st-order filter, a comparator and a simple digital circuit and tunes /spl plusmn/28 % time-constant variation of filters within /spl plusmn/4.4 % accuracy. The AGC circuit adopts a novel feedforward technique with a digital timing control, which enables one-shot gain control and thus a fast settling.


IEEE Journal of Solid-state Circuits | 2004

0.18-/spl mu/m CMOS Bluetooth analog receiver with -88-dBm sensitivity

Willy Hioe; Kenji Maio; Takashi Oshima; Yoshiyuki Shibahara; Takeshi Doi; K. Ozaki; S. Arayashiki

A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-/spl mu/m bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimize noise, and an on-chip automatic tuner adjusts the filter frequency. Other features included a feedforward automatic gain control with rapid convergence. When connected to the digital demodulator of a BiCMOS Bluetooth transceiver, -88-dBm sensitivity was measured at 65-mW power dissipation. All blocking signal specifications were also satisfied.


IEEE Transactions on Applied Superconductivity | 1995

Operation of a 1-bit quantum flux parametron shift register (latch) by 4-phase 36-GHz clock

Mutsumi Hosoya; Willy Hioe; Kazumasa Takagi; Eiichi Goto

The Quantum Flux Parametron (QFP) is a SFQ-type logic device which uses a single flux quantum (SFQ) to represent 1-bit of information. QFP circuits use a multi-phase external ac power which also acts as the clock for synchronization, hence QFP circuits are highly pipelined. The clock frequency must be increased to improve the throughputs of the circuits, so the control of a high frequency clock is a key technology for the QFP. This paper describes a clock distribution technique which utilizes the characteristics of a standing wave. Using this technique, the operation of a 1-bit QFP shift register by a 4-phase clock up to 36 GHz is shown. In the 4-phase clock operation of QFPs, the input is given in phase 1, the QFP switches in phase 2, the output is held during phase 3, and the QFP resets in phase 4. Therefore, the 4-phase 36-GHz operation means that each QFP switches or resets in less than 7 ps.<<ETX>>


international solid-state circuits conference | 2006

Wideband Image-Rejection Circuit for Low-IF Receivers

Koji Maeda; Willy Hioe; Yasuyuki Kimura; Satoshi Tanaka

A wideband image-rejection circuit for GSM/EDGE low-IF receivers includes a reference signal source and digital correction circuit that compensate I/Q gain, phase, and frequency response mismatch. The chip integrates an LNA, mixers, PGAs, LPFs, and fractional-N synthesizer in a 0.25mum BiCMOS process and achieves 50dB IRR over the entire signal bandwidth at 200kHz IF


IEEE Transactions on Applied Superconductivity | 1993

Margin analysis of quantum flux parametron logic gates

Mutsumi Hosoya; Willy Hioe

An analytical approach is used to estimate the (quasi-static) margins of quantum flux parametron (QFP) logic gates. The operation of a single QFP is analyzed in detail, and input biases or output variations caused by parameter fluctuations are obtained. The results are used to estimate the margins and yields of the QFP logic gates. The relations between the margin and the parameter fluctuations are obtained. The yields are estimated assuming normal distributions of the fluctuations. The calculations are consistent with experiments performed to date. The static margins of the QFP logic gates discussed here are sufficient, with presently available process technology, for medium size integrated circuits.<<ETX>>


Quantum flux parametron: a simple quantum flux superconducting logic device | 1991

Quantum flux parametron: a simple quantum flux superconducting logic device

Willy Hioe; Eiichi Goto

This book concerns a Josephson device for supercomputers which has extremely low heat dissipation (about 106 times less than semiconductor devices and 103 times less than voltage-based Josephson devices). In the previous book on Quantum Flux Parametrons (QFPs), DC Flux Parametron, the basic device operation are described. This book deals in much greater depth on the problems which are faced by the QFP. The device characteristics are worked out in detail showing clearly the analysis methods used. A new logic gate using the QFP is described with respect to its basic scheme, operation, and ways for forming logic circuits. The problems faced by the basic QFP are much reduced in the new logic gate. As the QFP operates near the Heisenberg and Boltzmann limits for computing devices, we also show the relationship between speed and stability. The book contains the latest analytical results on QFPs.The material presented in the book can be understood with very little mathematical training or knowledge about superconducting physics. It is also self-contained and does not require reading of other material. Most of the device characteristics can be reproduced from the equations given using simple programs. A circuit simulator is not needed except for high speeds when transient behavior becomes important.

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