Simon Haene

VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concurrent iterative sorting during the QR decomposition introduces a moderate overall latency, but provides the base for an improved layered stream decoding. This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers. The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization

When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MIMO-OFDM transceiver capable of transmitting 216 Mbit/s in 20 MHz bandwidth. The paper covers all parts of the system from RF to channel decoding and considers both algorithm and implementation aspects. In particular, we discuss the initial parameter estimation, channel estimation, MIMO detection, parameter tracking, and channel decoding. FPGA implementation results are reported along with measurements that demonstrate the throughput of spatial multiplexing with four spatial streams.

Towards an AES crypto-chip resistant to differential power analysis

Differential power analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher-key. Cryptographic security gets compromised if the current waveforms so obtained correlate with those from a hypothetical power model of the circuit. Such correlations can be minimized by masking datapath operations with random bits in a reversible way. We analyze such countermeasures and discuss how they perform and how well they lend themselves to being incorporated into dedicated hardware implementations of the advanced encryption standard (AES) block cipher. Our favorite masking scheme entails a performance penalty of some 40-50%. We also present a VLSI design that can serve for practical experiments with DPA.

OFDM channel estimation algorithm and ASIC implementation

Coherent detection of OFDM signals requires channel state information which can be acquired by transmitting known training symbols and by appropriate channel estimation at the receiver. Focusing on robust algorithms suitable for integration in silicon, a novel channel estimation method is proposed. The algorithm is based on a suboptimal modification to the maximum-likelihood estimator and was designed to enable the use of highly optimized constant-coefficient multipliers that require less area on silicon compared to regular multipliers. The mean square error and the complexity of different estimators are analyzed analytically, while an actual ASIC implementation allows to assess the real-world silicon area requirements for our proposed algorithm.

Low complexity frequency domain equalization of MIMO channels with applications to MIMO-CDMA systems

CDMA and MIMO-CDMA systems using RAKE receivers are heavily limited by self- and multiple-access-interference. Linear equalization is a means to remove this interference; however, it is often not practical due to the enormous complexity, especially in the MIMO case. The paper presents an approach to reduce greatly the complexity of linear MIMO equalizers. It discusses the complexity reduction of the equalizer itself and describes a suboptimal low-complexity method to compute its coefficients. The application of frequency domain equalization, using the overlap/add FFT method, to MIMO systems is suggested. The coefficients of the joint equalizer/MIMO detector are also derived in the frequency domain, based on an approximation of an MMSE criterion. Performance results in terms of BER are quantified through simulations of a MIMO-extended UMTS-FDD downlink.

FPGA Implementation of Viterbi Decoders for MIMO-BICM

The FPGA implementation of Viterbi decoders for multiple-input multiple-output (MIMO) wireless communication systems with bit-interleaved coded modulation (BICM) and per-antenna coding is considered. The paper describes how the recursive add-compare-select (ACS) unit, which constitutes the performance bottleneck of the circuit, can be pipelined to increase the throughput. As opposed to employing multiple parallel decoders, silicon area (resource utilization on the FPGA) is significantly reduced. The proposed optimizations lead to an implementation that achieves a throughput of 216 Mbps in a 4 times 4 MIMO-WLAN system prototype based on IEEE 802.11a

An automatic gain controller for MIMO-OFDM WLAN systems

MIMO-OFDM based wireless LAN standards are currently being defined. These systems employ packed-based communication, which requires fast and accurate automatic gain control. The precise estimation of the expected receive signal power of data symbols, based on preamble symbols is required in order to optimally detect the data signals. In this paper, two different preamble OFDM-symbols are considered and analyzed with regards to their suitability for received signal power estimation in MIMO-OFDM systems. An AGC architecture for an IEEE 802.11a based MIMO system is proposed and FPGA implementation results are reported.

FFT Processor for OFDM Channel Estimation

Pilot-assisted channel estimation for communication systems employing orthogonal frequency division multiplexing modulation requires significant signal processing at the receiver if the correlation among the frequency-domain channel coefficients is to be exploited in order to improve accuracy. In this work, a conventional FFT processor is extended to support all operations required by a selected channel estimation algorithm, so that both OFDM de/modulation and channel estimation can be efficiently performed on the same hardware unit. The silicon complexity of the extended processor, which was prototyped in a real-time testbed using FPGAs, is compared to a conventional FFT processor.

Simulation and emulation of MIMO wireless baseband transceivers

The development of state-of-the-art wireless communication transceivers in semiconductor technology is a challenging process due to complexity and stringent requirements of modern communication standards such as IEEE 802.11n. This tutorial paper describes a complete design, verification, and performance characterization methodology that is tailored to the needs of the development of state-of-the-art wireless baseband transceivers for both research and industrial products. Compared to the methods widely used for the development of communication research testbeds, the described design flow focuses on the evolution of a given system specification to a final ASIC implementation through multiple design representations. The corresponding verification and characterization environment supports rapid floating-point and fixed-point performance characterization and ensures consistency across the entire design process and across all design representations. This framework has been successfully employed for the development and verification of an industrial-grade, fully standard compliant, 4-stream IEEE 802.11n MIMO-OFDM baseband transceiver.