David Perels

VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concurrent iterative sorting during the QR decomposition introduces a moderate overall latency, but provides the base for an improved layered stream decoding. This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers. The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization

When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MIMO-OFDM transceiver capable of transmitting 216 Mbit/s in 20 MHz bandwidth. The paper covers all parts of the system from RF to channel decoding and considers both algorithm and implementation aspects. In particular, we discuss the initial parameter estimation, channel estimation, MIMO detection, parameter tracking, and channel decoding. FPGA implementation results are reported along with measurements that demonstrate the throughput of spatial multiplexing with four spatial streams.

Low complexity frequency domain equalization of MIMO channels with applications to MIMO-CDMA systems

CDMA and MIMO-CDMA systems using RAKE receivers are heavily limited by self- and multiple-access-interference. Linear equalization is a means to remove this interference; however, it is often not practical due to the enormous complexity, especially in the MIMO case. The paper presents an approach to reduce greatly the complexity of linear MIMO equalizers. It discusses the complexity reduction of the equalizer itself and describes a suboptimal low-complexity method to compute its coefficients. The application of frequency domain equalization, using the overlap/add FFT method, to MIMO systems is suggested. The coefficients of the joint equalizer/MIMO detector are also derived in the frequency domain, based on an approximation of an MMSE criterion. Performance results in terms of BER are quantified through simulations of a MIMO-extended UMTS-FDD downlink.

FPGA Implementation of Viterbi Decoders for MIMO-BICM

The FPGA implementation of Viterbi decoders for multiple-input multiple-output (MIMO) wireless communication systems with bit-interleaved coded modulation (BICM) and per-antenna coding is considered. The paper describes how the recursive add-compare-select (ACS) unit, which constitutes the performance bottleneck of the circuit, can be pipelined to increase the throughput. As opposed to employing multiple parallel decoders, silicon area (resource utilization on the FPGA) is significantly reduced. The proposed optimizations lead to an implementation that achieves a throughput of 216 Mbps in a 4 times 4 MIMO-WLAN system prototype based on IEEE 802.11a

An automatic gain controller for MIMO-OFDM WLAN systems

MIMO-OFDM based wireless LAN standards are currently being defined. These systems employ packed-based communication, which requires fast and accurate automatic gain control. The precise estimation of the expected receive signal power of data symbols, based on preamble symbols is required in order to optimally detect the data signals. In this paper, two different preamble OFDM-symbols are considered and analyzed with regards to their suitability for received signal power estimation in MIMO-OFDM systems. An AGC architecture for an IEEE 802.11a based MIMO system is proposed and FPGA implementation results are reported.

Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems

Multiple-input multiple-output (MIMO) communication systems require well-designed synchronization schemes in the receiver to meet stringent QoS requirements. In particular, OFDM modulation is very sensitive to timing synchronization errors, which cause inter-symbol interference. This paper describes a frame-start detection algorithm, which relies on received signal power increase and does not require any special properties of the transmitted signal. The performance is analyzed and then, verified through simulations in a MIMO system employing orthogonal frequency division multiplexing. Finally, a low-complexity FPGA implementation of the presented algorithm is described in detail.

Silicon Implementation of the SPIHT Algorithm for Compression of ECG Records

Wavelet algorithms with subsequent encoders are used in the newest image compression standards such as JPEG2000 including EBCOT. The set partitioning in hierarchical trees (SPIHT) algorithm belongs to the next generation of encoders for wavelet-transformed images employing more sophisticated coding. SPIHT utilizes inherent redundancy among wavelet coefficients and is especially suited for electrocardiogram (ECG) data and color image compression. In this work, we present the first VLSI implementation using a modified SPIHT algorithm (MSPIHT). Compression ratios of up to 20:1 for ECG signals lead to acceptable results for visual inspection by medical doctors.

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM

The performance of systems employing bit-interleaved coded modulation (BICM) critically depends on the availability of soft information. In the multi-antenna case, the extraction of optimum bit-metrics becomes prohibitively complex, so that suboptimal solutions need to be adopted for practical implementation. Instead of considering all the spatially multiplexed streams jointly, the implementation presented in this paper computes the soft information on each data stream separately, based on the output of an MMSE equalizer

A Frame-Start Detector for a 4×4 MIMO-OFDM System

Future wireless LANs will increase the peak data rate by employing multiple antennas at both transmitter and receiver. Well designed synchronization algorithms are a prerequisite for meeting stringent QoS requirements. In particular OFDM modulation, which constitutes the basics for WLAN, is very sensitive to timing synchronization errors which incur inter-symbol interference. In this paper, a novel frame synchronization algorithm is proposed that is implemented in the FPGA of a real-time MIMO-OFDM testbed. Simulations show it to be of sufficient performance in scenarios of interest, while the hardware complexity is suitable for an FPGA implementation. Additionally, the algorithm exhibits a good resilience against narrow-band interference, which causes problems in traditional frame-start detection algorithms.