Woojin Lee

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer

In this paper, we present a lumped element model for coupled interconnect structures of TSV, metal interconnects, and Redistribution Layer (RDL) in Through-Silicon-Via (TSV)-based 3D IC with silicon interposer. We also analyzed the electrical characteristic of coupling between 3D silicon interposer interconnects. The equivalent lumped model is derived and verified with the S-parameter measurement results. The lumped model for TSV, metal, and RDL combined interconnects is verified with the EM solver simulation results. The S-parameter from the proposed model shows good agreement with the result from the measurement and simulation up to 20GHz. We also proposed shielding structures to suppress coupling between silicon interposer interconnects.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structures impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

Thermal characterization of thermally conductive underfill for a flip-chip package using novel temperature sensing technique

The thermal characteristics of thermally conductive underfill in flip chip package was studied. To enhance the thermal conductivity of underfill, the epoxy was mixed with thermally conductive fillers, such as silica (1.5W/mK), alumina (36W/mK), or diamond (2000W/mK). Coefficient of thermal expansion (CTE) was changed by filler and its content, and CTE was 28 ppm for 60 wt% silica, 39 ppm for 60 wt% alumina and 24 ppm for 60 wt% diamond. Thermal conductivity was calculated from the measurement of thermal diffusivity, density and specific heat capacity under the various temperature conditions with the various fillers. To investigate thermal characteristics of different underfill, diode temperature sensor array (DTSA) was fabricated, which consists of 32 by 32 array of diodes (1,024 diodes) for temperature measurement and 8 heaters for heat source on a 8mm by 8mm of silicon surface. The DTSA was packaged by flip chip packaging method and applied with the same power (0.84W) for different underfilled packages. Finally, the thermal simulations with ICEPAK matched very well with the measurement

Analysis of power distribution network in TSV-based 3D-IC

To reduce simultaneous switching noise (SSN) in a PDN design of TSV-based GPU system, the impedance properties of the hierarchical PDN in the TSV-based GPU system were estimated and analyzed. The system consisted of triple-stacked TSV-based DRAMs on top of the GPU connected by TSVs, a silicon interposer, and a backside re-distribution layer (BS-RDL). A segmentation-based impedance-estimation method was used for the estimation of the total PDN impedance combining models of the on-chip PDN, the power/ground (P/G) TSV, and the coplanar P/G line in the BS-RDL. The impedance properties of the PDN were also analyzed with respect to variations in the number of P/G TSVs and P/G lines in the BS-RDL and variation of the capacitance of the on-chip decoupling capacitor embedded in the on-chip PDN.

A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

A compact wide-band passive equalization design using a stub with defected ground structure is proposed. The proposed design, based on reflections under a slow wave effect, compensates for inter-symbol interference with wide bandwidth, compact size, remarkable compensation capability with few manufacturing limitations, and high design flexibility, compared to previous equalization design. Significant improvements in eye-opening and timing jitter are successfully demonstrated for a data rate of 8 Gbps for a 60 cm transmission line on a printed circuit board.

A Wide-Band Passive Equalizer Design on PCB Based on Near-End Crosstalk and Reflections for 12.5 Gbps Serial Data Transmission

We propose a wide-band passive equalization method for high-speed serial chip-to-chip input/output channels using wave propagation, reflection, and coupling effects on a tightly coupled transmission line structure. This design offers precise control of wideband equalization and low-power consumption as compared to previous active and discrete passive equalizers. Significant improvements in timing jitter and voltage margin are successfully demonstrated for a data rate of 12.5 Gbps on a 40 cm long backplane printed circuit board.

Power/ground noise immunity test in wireless and high-speed UWB communication system

This paper presents a wireless and high-speed transceiver system for Ultra-Wideband (UWB) communication with a high noise immunity. A proposed transceiver system has a high-speed data transmission up to 130 Mbps. Then, the measurement setup for the noise immunity test is introduced. Also, in order to demonstrate a noise immunity of the system, timing jitter, accumulated waveform, and bit error rate (BER) are measured in the presence of a power/ground noise with various frequencies or amplitudes. The numerous measurement results help to understand the relationship between the power/ground noise and the noise immunity of the proposed transceiver system.

Hybrid modeling and analysis of power supply noise effects on analog-to-digital converter considering hierarchical PDNs

An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the circuit through the hierarchical PDN structure in multilayer PCB substrates. In this paper, a hybrid model is proposed for analysis of power supply noise effects on the ADC. The model combines two modeling mechanisms. First, the coupling ratio of the power supply noise is derived by the combined model of hierarchical PDNs at the PCB and the chip. Second, an analytical model is proposed using equivalent circuits for analysis of the power supply noise effects on the ADC. The ADC is designed using a 0.13um CMOS process. The proposed model and analysis are verified based on a simulation from 100kHz to 4GHz. The performance of the ADC is dominantly affected by characteristics of the on-chip circuit under 100MHz. It is also confirmed that the Effective Number of Bits (ENOB) of the ADC is strongly dependent on the hierarchical PDN impedance over 100MHz. Furthermore, there are peak points caused by inter-modulation (IMD) and cavity resonances of PDN structures.

A frequency tunable resonant clock distribution scheme using bond-wire inductor

In this paper, we propose a frequency control method for a resonant clock distribution scheme using a bond-wire inductor. The resonant clock distribution using the embedded planes in a package and an inductive load suppresses the clock source jitter and significantly reduces the clock skew by replacing the cascaded repeaters of a conventional on-chip clock distribution. The resonant frequency can be controlled by the inductance of the load and the size of cavity planes. We use a bond-wire inductor instead of a chip inductor for fine tuning of resonant frequency and reducing the parasitic capacitance of integration. We have successfully demonstrated a 1.35 GHz clock delivery network with the transmission line matrix model of the plane cavity and the lumped model of bond-wire inductor. The simulation results show that the source jitter is suppressed by the resonance effect and the skew is minimized and the frequency is controlled by the inductance of a bond wire.