Jongbae Park

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Double-Stacked EBG Structure for Wideband Suppression of Simultaneous Switching Noise in LTCC-Based SiP Applications

We propose a novel electromagnetic bandgap (EBG) structure with a significantly extended noise isolation bandwidth, called a double-stacked EBG (DS-EBG) structure, fabricated on a low-temperature co-fired ceramic (LTCC) multilayer substrate. The DS-EBG structure was devised for wideband suppression of simultaneous switching noise (SSN) coupling in system-in-package (SiP) applications. Our design approach was enabled by combining two EBG layers embedded between the power and ground planes. The two EBG layers had different bandgaps from using different cell sizes. Enhanced wideband suppression of the SSN coupling was validated using a 11.4-GHz noise stop bandwidth with 30-dB isolation in time and frequency domain measurements up to 20GHz

Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards

As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism was rigorously analyzed and clarified. Wave equations for a signal trace with power/ground noise were solved by imposing boundary conditions. Measurements in both the frequency and time domains have been conducted to confirm the validity of the proposed model.

Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor

Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.

Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

A new hybrid modeling method is proposed for the chip-package co-modeling and co-analysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mum. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package co-modeling and simulation of the system-in-package designs.

Accurate high frequency lossy model of differential signal line including mode-conversion and common-mode propagation effect

The loss in multilayer printed circuit boards (PCB) becomes a crucial problem and lacks precise models in high-speed interconnections such as the SerDes channel. Moreover, unbalanced and discontinuous structures generate undesirable mode-conversion, differential-to-common mode and common-to-differential mode. We have propose an accurate and efficient differential line model where all of the mode-conversion, common-mode propagation and frequency-dependent loss are taken into consideration over the GHz frequency range.

Noise coupling to signal trace and via from power/ground simultaneous switching noise in high speed double data rates memory module

We suggested the model to demonstrate simultaneous switching noise (SSN) coupling to signal and verified experimentally. There are two coupling mechanisms; one is the SSN coupling through the reference changing via, and the other is the SSN coupling through the signal trace. Through measurement and analysis, we confirmed that the worst SSN coupling occurs when strip lines have the signal via changing reference plane with SSN. Furthermore, we demonstrated that the power/ground noise coupling to the signal is reduced by placing the reference changing via at the position where the power/ground cavity impedance is low, or by adjusting the line length between two reference changing vias.

Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB

The return current path is the most critical part of high-speed interconnection design in both package and PCB. When the return current path is disturbed, significant amount of noise generation, coupling, and radiated emission problems occur. Signal vias and power/ground vias produce a return current path disconnect problem. In this paper, we demonstrate that the via is a major source of the SSN (simultaneous switching noise) generation, coupling, and edge radiated emission in multi-layer packages and PCBs.

Characterization of SSN coupling to signal via in multi-layer PCBs and packages

The signal via is a heavily utilized interconnection structure in high-density system-on-package (SoP) substrates and PCBs. Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER) and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by the frequency domain measurements of several via transition structures

Analysis of noise isolation methods on split power/ground plane of multi-layered package and PCB for low jitter mixed mode system

Various noise isolation methods for low jitter on the power/ground plane are thoroughly analyzed and a new method is proposed. We analyzed using both frequency and time domain measurement methods and the results were verified by jitter measurements.