Wook Lee

A high fill-factor infrared bolometer using micromachined multilevel electrothermal structures

A high fill-factor uncooled infrared (IR) bolometer has been fabricated by using thin-film titanium resistors sandwiched in a surface-micromachined silicon oxinitride membrane (50 /spl mu/m/spl times/50 /spl mu/m). This bolometer is realized in multilevel electrothermal structures with a fill-factor over 92%. From the multilevel structure, thermal isolation can be independently optimized without sacrificing IR absorbing area. Initial measurements show a thermal time constant of 12 ms, a responsivity of 1600 V/W, and a detectivity (D*) of 5/spl times/10/sup 8/ cm/spl radic/Hz/W.

The effect of dimensional scaling on the erase characteristics of NOR flash memory

In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.

Post-cycling data retention failure in multilevel nor flash memory with nitrided tunnel-oxide

Post-cycling data retention characteristics of a multilevel NOR flash memory with nitrided tunnel-oxide is presented. Results show that retention behavior is strongly related to the amount of interface trap generation rather than that of oxide trap, indicating detrapping from near interface trap is a major factor for threshold voltage shift. Process conditions including nitrogen concentration at the interface and subsequent annealing of nitrided tunnel-oxide by O2 are found to be related to the generation of interface trap and resultant postcycling retention.

Temperature Dependence of Endurance Characteristics in NOR Flash Memory Cells

A temperature dependence of endurance characteristics in NOR flash cells is presented. The window closing is accelerated after 100 K cycling due to a degraded programming speed at 85 degC compared to that measured at 25 degC. At 25 degC, both oxide traps and interface traps reduce program and erase speeds, while at 85 degC the effects of interface traps generated at the drain overlap region become increased, interrupting the hot electron injection during program operation. Two processing conditions including growth condition of tunnel oxide and the type of passivation layer are found to be related to the degradation of endurance

Mobile ion-induced data retention failure in NOR flash memory cell

Data retention failures due to nonoptimized processes in NOR-type flash memory cells are presented. Contrary to the charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. It is found that the data loss exhibits a charge-state dependence during baking stresses as well as temperature dependence. Based on experimental results, sodium movement in sidewall spacers is established as an origin for the data retention failure in NOR-type flash memory cells. Employing a thin nitride overlayer results in a good data retention, supporting the hypothesis of sodium movement.

A high fill-factor IR bolometer using multi-level electrothermal structures

In this paper we report the design, fabrication, and performance of a high fill-factor uncooled IR (Infrared) bolometer using thin-film titanium resistors sandwiched in a surface-micromachined silicon oxynitride membrane (50 /spl mu/m /spl times/50 /spl mu/m). This bolometer structure comprises multi-level electrothermal structures, which allow almost 92% fill factor. From this multi-layered structure, thermal isolation can be independently optimized without sacrificing IR absorbing area. Initial measurements show a thermal time constant of 12 msec, a responsivity of 1600 V/W, and a detectivity of D*=5/spl times/10/sup 8/ cm/spl radic/(Hz)/W.

Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile

We present a comparative investigation of two self-aligned processes, viz. Self-Aligned Poly (SAP) and Self-Aligned STI (SA-STI) for high-density flash memory cells. SAP is shown to lead to narrow erase Vth dispersion and better endurance reliability via the control of oxide edge profile. The erase Vth dispersion is systematically simulated vs. process variations, confirming the sensitive role of edge profile in affecting F-N tunneling current. We also present a successful operation of 256Mb NOR flash MLC, fabricated with a 90 nm technology by SAP process.

A New Failure Mechanism of MLC NOR Flash Memory Caused by Aggravated Drain Disturb Due to Co-Salicidation Process

We report a new failure mode of multi-level cell (MLC) NOR flash memory induced by anomalously increased drain disturb. The aggravated disturb, occurring in ppm level, is shown to be caused by an abnormal lateral encroachment of cobalt silicide on the drain side of the NOR flash cell. The failure mode, which becomes more critical as the NOR flash cell scales down, can be alleviated by optimizing the thickness of cobalt salicidation and controlling the defect density induced by spacer etch and ion implantation on the drain side

New Floating Gate Self-Aligning Technology for Multilevel NOR Flash Memory

This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good buffer layer to prevent the oxide local thinning at STI corners of both cell and peripheral areas. Using the poly-Si as a sacrificial-layer during tunnel oxide growth, a 65nm NOR flash memory with a cell size of 0.039 mum2 has been developed and achieved the multilevel cell (MLC) operation. Also, an improved post-cycled retention characteristics has been obtained

Advanced image sensor technology for pixel scaling down toward 1.0µm (Invited)

As pixel size of image sensors shrinks down rapidly, we are reaching technical barrier to get the required low light performance. In this paper, recent advanced technologies such as backside illumination, new color filter array, low F-number with extended depth of field technologies, etc. are introduced to overcome such a barrier. It is shown that the integration of these advanced sensor technologies can make pixel size shrink down toward 1.0 mum with the required performance.