Sang-pil Sim

A 14 nm FinFET 128 Mb SRAM With V

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm2 and a 0.080 μm2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the VMIN of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 VMIN with 200 mV improvement by NBL, and 0.47 VMIN for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved VMIN reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

_{\rm MIN}

We report a Planar Stack Technology (PST) suitable for scaling and combining DRAM with logic circuits. Key features of PST technology are retrograde twin well, shallow trench isolation (STI), self-aligned poly plug structure, damascene W bit-line, Ta/sub 2/O/sub 5/ capacitor dielectric and planarized capacitor formation. This new architecture provides planar surfaces for all the lithographic steps and is easy to combine CMP-based backend processes. Although the process margin and electrical performance are proven using full density, 256 M DRAM chip, this technology can be applied to 1 G bit DRAM and beyond with simple photo lithographic scaling.

Enhancement Techniques for Low-Power Applications

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

A new planar stacked technology (PST) for scaled and embedded DRAMs

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

For the first time, a fully 3-dimensional (3-D) flash cell with recessed channel and cylindrical floating gate is successfully integrated with 65nm MLC NOR flash technology. Key process technologies to achieve the novel cell structures are shown to be highly feasible. Superior scalability and comparable device characteristics including V th distribution and tunnel oxide reliability are proved through 512Mb full chip integration. Intrinsic immunity on the short channel effect of this 3-D cell opens a promising path for the continued scaling of the floating gate flash memories for 65nm and beyond

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 70nm NOR flash technology has been for the first time developed with a cell size of 0.0494m, which is the smallest size of NOR flash cell, for high density memory of mobile application. The operation of 0.049PM cell transistor is successfully achieved with three key technologies such as an optimized Self-Aligned Poly (SAP) structure with top corner rounding trench structure, a cell drain contact process by ArF photo lithographic tool, and a cell transistor with a gate length of 120nm.

Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.

A 70nm NOR flash technology with 0.049 /spl mu/m/sup 2/ cell size

We present a comparative investigation of two self-aligned processes, viz. Self-Aligned Poly (SAP) and Self-Aligned STI (SA-STI) for high-density flash memory cells. SAP is shown to lead to narrow erase Vth dispersion and better endurance reliability via the control of oxide edge profile. The erase Vth dispersion is systematically simulated vs. process variations, confirming the sensitive role of edge profile in affecting F-N tunneling current. We also present a successful operation of 256Mb NOR flash MLC, fabricated with a 90 nm technology by SAP process.

13.2 A 14nm FinFET 128Mb 6T SRAM with V MIN -enhancement techniques for low-power applications

We report a new failure mode of multi-level cell (MLC) NOR flash memory induced by anomalously increased drain disturb. The aggravated disturb, occurring in ppm level, is shown to be caused by an abnormal lateral encroachment of cobalt silicide on the drain side of the NOR flash cell. The failure mode, which becomes more critical as the NOR flash cell scales down, can be alleviated by optimizing the thickness of cobalt salicidation and controlling the defect density induced by spacer etch and ion implantation on the drain side

Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile

This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good buffer layer to prevent the oxide local thinning at STI corners of both cell and peripheral areas. Using the poly-Si as a sacrificial-layer during tunnel oxide growth, a 65nm NOR flash memory with a cell size of 0.039 mum2 has been developed and achieved the multilevel cell (MLC) operation. Also, an improved post-cycled retention characteristics has been obtained