Heon Kyu Lee

Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

For the first time, a fully 3-dimensional (3-D) flash cell with recessed channel and cylindrical floating gate is successfully integrated with 65nm MLC NOR flash technology. Key process technologies to achieve the novel cell structures are shown to be highly feasible. Superior scalability and comparable device characteristics including V th distribution and tunnel oxide reliability are proved through 512Mb full chip integration. Intrinsic immunity on the short channel effect of this 3-D cell opens a promising path for the continued scaling of the floating gate flash memories for 65nm and beyond

Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile

We present a comparative investigation of two self-aligned processes, viz. Self-Aligned Poly (SAP) and Self-Aligned STI (SA-STI) for high-density flash memory cells. SAP is shown to lead to narrow erase Vth dispersion and better endurance reliability via the control of oxide edge profile. The erase Vth dispersion is systematically simulated vs. process variations, confirming the sensitive role of edge profile in affecting F-N tunneling current. We also present a successful operation of 256Mb NOR flash MLC, fabricated with a 90 nm technology by SAP process.

A New Failure Mechanism of MLC NOR Flash Memory Caused by Aggravated Drain Disturb Due to Co-Salicidation Process

We report a new failure mode of multi-level cell (MLC) NOR flash memory induced by anomalously increased drain disturb. The aggravated disturb, occurring in ppm level, is shown to be caused by an abnormal lateral encroachment of cobalt silicide on the drain side of the NOR flash cell. The failure mode, which becomes more critical as the NOR flash cell scales down, can be alleviated by optimizing the thickness of cobalt salicidation and controlling the defect density induced by spacer etch and ion implantation on the drain side

A 90nm generation NOR flash multilevel cell (MLC) with 0.44/spl mu/m/sup 2//bit cell size

A 256Mb NOR MLC flash memory with 90nm technology has been successfully developed. Through judicious integration to control the cell dispersion and charge loss/gain with cycling, we confirm a successful MLC operation up to 10K cycling for 0.44 /spl mu/m/sup 2//bit cell size. In this paper, the key features governing multilevel cell (MLC) operation below 90nm technology node is discussed with experimental results.

Tunnel Oxide Optimization to Improve Post-Cycling Retention of Flash Memories

To improve post-cycling retention of Flash memory, we present NO re-oxidation technique for tunnel oxide growing. We demonstrate that the quality of NO re-oxidation tunnel oxide is superior to that of conventional NO annealing oxide. The quality of NO re-oxidation is strongly affected by NO concentration and re-oxidation thickness. Using well-optimized NO re-oxidation, we accomplish successful operation of 512Mb NOR Flash in a 65nm technology, satisfying highly reliable retention characteristicᄂ as well. Introduction Program/erase cycling of Flash memories causes damage to the tunnel oxide in the form of neutral and charged bulk traps and interface states. When charges are detrapped, charge trapping at the interface traps and oxide bulk can cause threshold voltage shifts in post-cycling retention tests [1]. To improve the characteristic of post-cycling retention, the nitride treatments of tunnel oxide are mainly obtained by annealing the oxide in NO or N2O ambient [2], [3]. In this work, we suggest another novel method for tunnel oxide nitridation; ‘NO re-oxidation’. We demonstrate that the quality of NO re-oxidation oxide is superior to that of NO annealing oxide. Furthermore, the quality of NO re-oxidation oxide is found to be strongly affected by NO concentration and re-oxidation thickness. Experiment Devices were fabricated with 65nm NOR technologies. 10K cycles of program/erase were performed with retention bake at 200°C. Data were collected from a 512K bits array. The threshold voltage shifts due to the cycling and bake were measured in a 512K bits array. The I-V characteristics of the single cell were measured before and after the cycling stress. Results The programmed Vth dispersion (“10” and “01” states in multi-level cell) measured from 512K cells after 10K cycles and post-cycling bake are shown in Fig. 1 and Fig. 2, respectively. The Vth shifts after post-cycling bake resulting from NO re-oxidation are smaller than that from NO tunnel oxide. This can be understood in correlation with the difference in the quality of tunnel oxide. Fig. 3 shows the endurance characteristics of the cells where the program and erase operation are done by channel hot electron injection and channel F-N tunneling, respectively. The upward shift of the erase Vth of NO re-oxidation is larger compared with the NO annealing oxide. Fig. 4 shows the drain current as a function of the gate voltage for both NO annealing and NO re-oxidation oxides. The Vth shift and the sub-threshold swing degradation after endurance is smaller for the case of NO re-oxidation. Clearly, the NO re-oxidation oxide exhibits the advantages in endurance characteristics over NO anneal oxide. Fig. 5 and Fig. 6 show the endurance characteristics for NO re-oxidation in different conditions. (NO Re-Ox.(I) and NO Re-Ox.(II)). From the Id-Vg plot, the Vth shifts for NO re-oxidation are exceptionally sensitive to the growing condition. It implies that the careful engineering of the NO re-oxidation process can further improve the quality of tunnel oxide. Fig. 7 shows the post cycling retention data for different tunnel oxides, in which each point represents Vth shift (∆ VT,Lowest in Fig.1 and Fig. 2) of the worst bit in 512K bits. The ∆ VT,Lowest by NO re-oxidation is reduced compared to the normal NO annealing oxide. The improvement is even more evident for the well-optimized NO re-oxidation oxide, i.e. NO Re-Ox. (II) in Fig. 7. Fig. 8 shows the ∆ VT,Lowest as a function of the re-oxidation thickness for the samples processed with different concentration of NO ambient. The increment in re-oxidation thickness leads to significant improvement in the post cycling retention. However, the further increases the re-oxidation thickness up to the certain point, the more increases ∆ VT,Lowest in the post cycling retention. It indicates that there is an optimum thickness of the NO re-oxidation for the best retention characteristic. Moreover, increasing nitrogen incorporation in NO annealing process also ameliorates the post cycling retention. Analysis Trapped charge during endurance alters the I-V characteristics. The interface trapping can be measured by the change of the sub-threshold swing and the Vth shifts denoted by ∆ VT,Nit . If the total Vth shift after endurance is ∆ VT,total, the Vth shift by oxide bulk trap (∆ VT,Not) can be represent by ∆ VT,Not = ∆ VT,total ∆ VT,Nit. The ∆ VT,Lowest in the post cycling retention is caused by electron detrapping from interface and oxide bulk trap. Thus, the ∆ VT,Lowest is proportional to the total amount of charge trapped during cycling. Fig. 9 shows the ∆ VT,Lowest by oxide bulk traps vs. re-oxidation thickness and NO ambient. It can be seen that the Vth shift by oxide traps maintains constant value up to certain thickness, while more re-oxidation give rise to significant increasing of Vth shift. On the other hand, as shown Fig. 10, increasing re-oxidation thickness rapidly reduces the Vth shift by interface traps. These results can be explained with a two-step mechanism of NO re-oxidation [3]. First, there is an initial reaction between the incoming O2 and the nitride layer at the interface, such reaction is interface limited. Thus, increasing re-oxidation thickness can reduce interface trap only. However, with increasing the re-oxidation thickness up to certain value, the reaction between O2 and the nitride layer is ended, and the additional oxide is grown. This unwanted oxide contains many bulk trap sites, since nitrogen-related bonds replace Si-O bonds in the oxide bulk and hence weaken the oxide structure. Thus, as shown Fig. 8, we appreciate that the initial reliability improvement in region “A” is caused by the decrease of interface traps and the reliability degradation in region “B” is caused by the increase of oxide bulk traps. Fig. 11 shows the contribution portion for the Vth shifts by interface traps, oxide traps and NO concentration. As the NO concentration increases, the interface traps exponentially decrease, and then only the oxide bulk traps remains. Therefore, the oxide bulk traps are the major contributor to Vth shift. Conclusion We show that the NO re-oxidation process improves the reliability of post-cycling retention. Moreover, using optimization of NO re-oxidation, we achieve highly reliable endurance and retention characteristics in 512M NOR MLC flash memory. References [1] Neal Mielke et al, IEEE Transaction on Device and Materials Reliability, p. 335~344, 2004 [2] D. Barzzeli et al, Solid-State Electronics, p. 1271~1278, 2001 [3] C. Gerardi et al, Micron, p. 291~292, 2000 Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -990F-7-5L pp. 990-991

Anomalous charge loss of reference cell in MLC flash memory due to process-induced mobile ion

This paper reports an anomalous charge loss observed from the reference cell of MLC flash memory induced by the cobalt salicide process. The reference cell is shown to exhibit unique retention behavior different from that of the normal array cell. Both the source and mechanism of the enhanced charge loss therein are investigated through various bake tests, mobile ion analysis, and structural analysis. A simple yet effective way to protect the reference cell from the process-induced mobile ions is proposed.