Woonghwan Ryu

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Microwave model of anisotropic conductive film flip-chip interconnections for high frequency applications

Microwave model and high-frequency measurement of the anisotropically conductive film (ACF) flip-chip interconnection was investigated using a microwave network analysis. The test integrated circuits (ICs) were fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process with an inverted embedded microstrip structure. As flip chip bumps, electroless Ni/Au plating was performed on Al input/output (I/O) pads of test IC chips, As an interconnect material, several ACFs were prepared and flip-chip bonded onto the Rogers(R) RO4003 high frequency organic substrate. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe, and the cascade transmission matrix conversion was performed. The same measurements and conversion were conducted on the test chip mounted substrates at the same frequency range. Then impedance values in flip-chip interconnection were extracted from cascade transmission matrix. The extracted model parameters of the 100 /spl mu/m/spl times/100 /spl mu/m interconnect pad show the resistance increases due to skin effect up to 8 GHz. Above this frequency, conductive loss of epoxy resin also increases. Reactance is dominantly affected by inductance of Ni/Au bumps and also conductive particles in the ACF interconnection over the measured frequency range. The inductance value of ACF flip chip interconnection is below 0.05 nH and the contact resistance is below 0.9 R. In addition, the effects of different ACF conductive particle materials on high frequency electrical behavior in GHz range were also investigated, Different ACF conductive particle materials show difference in the reactance, resistance, and resonance frequency behavior up to 13 GHz. Our results indicate that high frequency electrical performance of ACF combined with electroless Ni/Au bump interconnection is acceptable for use in the high frequency flip chip application up to 13 GHz. Finally, 80-ps rise time digital signal transmission with small dispersion low loss reflection was demonstrated through the flip-chip interconnection with combination of ACF and Ni/Au bump.

Embedded microstrip interconnection lines for gigahertz digital circuits

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements.

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time.

Separated role of on-chip and on-PCB decoupling capacitors for reduction of radiated emission on printed circuit board

The power/ground fluctuation is known as a significant source of radiated emission. We discuss the separated functions of on-PCB and on-chip decoupling capacitors on the suppression of electromagnetic radiated emission. Due to the different ranges of parasitic inductance and the different locations of the on-chip current drivers, on-PCB and on-chip decoupling capacitors exhibit separated frequency characteristics in terms of suppression efficiency of radiation. The roles of on-PCB and on-chip decoupling capacitors are estimated by circuit simulation and a simple antenna model, and are confirmed by experiments. It is found that the on-chip decoupling capacitors are mainly effective for the suppression of radiated emission over 100 MHz frequency. Increase of the on-chip decoupling capacitance and decrease of the parasitic inductance of the package produce an improved suppression ratio at high frequency range. Combined placement and sizing of the decoupling capacitors have achieved more than 10 dB suppression of the electromagnetic radiated emission over a wide spectrum range.

High-frequency SPICE model of anisotropic conductive film flip-chip interconnections based on a genetic algorithm

This paper firstly reports on the high-frequency SPICE model of the ACF flip-chip interconnections up to 13 GHz. The extraction process is based on an optimization procedure, called a genetic algorithm, which is known as a robust optimization tool. The proposed equivalent circuit model of the ACF interconnection can readily be used in SPICE circuit simulations for signal integrity analysis of high-frequency packages. Two different ACF interconnections were studied using the Au-coated polymer ball and Ni-filled ball. The extracted models of the two ACFs were found strongly dependent on not only size and rigidity of the conducting balls, but also on their magnetic permeability.

Reduction of crosstalk noise in modular jack for high-speed differential signal interconnection

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz.

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.

Microwave model of anisotropic conductive adhesive flip-chip interconnections for high frequency applications

Microwave model and high-frequency measurement of the ACF flip-chip interconnection is investigated using a microwave network analysis. The test IC was fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process with an inverted embedded microstrip structure. As flip chip bumps, electroless Ni/Au plating was performed on test IC chips and as an interconnect material, several ACFs were prepared and flip-chip bonded onto the Rogers(R) R04003 high frequency organic substrate. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. The cascade transmission matrix conversion was performed. The same measurements and conversion were conducted on the test chip mounted substrates at the same frequency range. Then impedance values in flip-chip interconnection were extracted from cascade transmission matrix. The extracted model parameters of the 100 /spl mu/m/spl times/100 /spl mu/m interconnect pad show the resistive increases due to skin effect up to 8 GHz; after this frequency, conductive loss of epoxy resin also increases. Reactance is dominantly affected by inductance of Ni/Au bumps and conductive particles in the ACF interconnection at whole measured frequencies. ACF flip chip interconnection has only below 0.1 nH. The effects of different conductive particle materials on electrical behavior in GHz were investigated. Different particle materials in ACF show the difference in the reactance and resistance behavior up to 12 GHz and in the resonance frequency. Our results indicate that the electrical performance of ACF combined with electroless Ni/Au bump interconnection is comparable to that of solder joint.