Myunghee Sung

Embedded microstrip interconnection lines for gigahertz digital circuits

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements.

Reduction of crosstalk noise in modular jack for high-speed differential signal interconnection

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz.

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.

A novel twisted differential line for high-speed on-chip interconnections with reduced crosstalk

Differential signaling has become a popular choice for high-speed interconnection schemes, offering superior immunity to external noise. However, conventional differential transmission lines still have problems, such as crosstalk and radiated emission. To overcome these, we propose a twisted differential line (TDL) structure. In this paper, experimental results of the proposed structure on a multi-layer PCB are summarized. Its improved immunity to crosstalk, and the reduced radiated emission have been successfully demonstrated. Furthermore, the TDL is firstly implemented on a chip and the preliminary results are reported. Finally, it is demonstrated that the proposed TDL delivers a promising solution for high-speed and high-density digital interconnection designs.

Design and analysis of improved multi-module memory bus using wilkinson power divider

Branch connections in multi-module memory bus are usually sources of impedance mismatching, resulting in resonance in the branch stub. An effective way has been proposed to reduce stub resonance by using Wilkinson power divider. The effect of Wilkinson divider has been verified by experiments in both frequency and time domains.

Suppression of radiated emission from an 8-bit micro-controller using gate-oxide filtering capacitors

The voltage fluctuations of the power/ground lines on ICs, packages, and modules have become the major source of the radiated emission. Combined suppression techniques including shielding, cabling and filtering at the package level and the module level are not enough for the complete suppression of radiated emission. Moreover, the power/ground line fluctuations and the resulted radiated emissions caused by the IC surge current must be controlled and considered at the IC design procedure. We have demonstrated more than 10-dB suppression of the radiated emission from a commercial 8-bit micro-controller using on-chip gate oxide filtering capacitors. The filtering capacitors are placed under the power/ground buses and the signal buses without ever increasing the die size.

Compensation of unbalanced capacitive crosstalk noise in category-5E modular jack using balancing capacitor in PCB

We have successfully designed a PCB substrate with the embedded balancing capacitors for the category-5E modular jack to compensate the unbalanced capacitive crosstalk noise. The NEXT (near-end crosstalk) after the crosstalk compensation is below -45 dB at 100 MHz.

An efficient crosstalk parameter extraction of embedded microstrip structures on high-speed MCM

In this paper, we firstly introduce a simplified and reliable approach for the extraction of the crosstalk model parameters of high-speed on-chip and MCM interconnection lines. The voltage coupling coefficient, the mutual capacitance and the mutual inductance can be easily extracted from the S-parameter measurement and time-domain reflection measurement. In contrast to the previous extraction procedures of the crosstalk models, the suggested extraction procedure not only requires less on-wafer probing steps but also is close to physical insight. Also the models can be easily applicable to the SPICE simulation. The validity of the extracted model was examined by comparing the time-domain crosstalk pulse measurement using the TDR/T to the time domain pulse waveforms calculated using the SPICE simulation using the extracted model parameters. The close agreement of the amplitude and the pulse shape was observed, indicating the preciseness of the extracted crosstalk model.

Differential-line-scheme of clock and signal bus of high-speed digital circuits and systems for minimizing electromagnetic radiated emission

Even though the electromagnetic radiated emission due to the ground and power line fluctuation of the integrated circuit (IC) and printed circuit board (PCB) is minimized, the additional reduction of the radiated emission from the clock and the signal lines are not easy. In this paper, we introduce a new clock and signal line scheme to suppress the radiated emission from the fast transition of the clock and data signals. We proved that the proposed differential-line-scheme (DLS) could reduce the radiated emission by more than 10 dB compared to the conventional single-line-scheme (SLS). First, we report the necessity and the usefulness of the differential-line-scheme and explain the operation of the inverter circuit for the differential-line-scheme using HSPICE simulation. Test ICs and PCBs were designed and fabricated, to verify the effect of differential-line-scheme with the proposed inverter circuit. The electromagnetic radiated emission due to the device under test (DUT) is measured using a gigahertz transverse electromagnetic (GTEM) cell. The measured result has shown that the differential-line-scheme with the proposed inverter circuit achieves more than 10 dB suppression of the electromagnetic radiated emission. The results confirm that the clock and signal line is fundamental source of the radiation. The proposed differential-line-scheme with the proposed inverter circuit will be useful for both high-speed digital IC and PCB design.