Xavier Aragonès

Analysis and solutions for switching noise coupling in mixed-signal ICs

1. Introduction. 2. Substrate noise characteristics and propagation. 3. Substrate coupling modeling. 4. Substrate biasing and noise coupling. 5. Alternative proposals for reducing substrate noise. 6. Experimental measurements performed on a mixed-signal IC. 7. The cause of switching noise. 8. Digital design for low switching noise. 9. Techniques and circuits for reducing switching noise. 10. Conclusions.

Experimental comparison of substrate noise coupling using different wafer types

Measurements of substrate coupled noise in a mixed-signal test IC are presented. This IC was manufactured with different types of wafers, and noise levels measured in heavily-doped epi wafers are about three times larger than those obtained in lightly doped ones. It is determined that, due to package parasitics, noise at the supply lines will easily be the major contributor to substrate-coupled disturbances, both at the digital and at the analog ends. Supply lines interact with the substrate mainly through the substrate contacts of both of the circuit core and the ring of pads. The measurements contribute to establishing a list of priorities in the actions to reduce the noise that reaches the analog section.

Noise generation and coupling mechanisms in deep-submicron ICs

On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms.

Substrate coupling evaluation in BiCMOS technology

The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-/spl mu/m BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring.

Phase noise degradation of LC-tank VCOs due to substrate noise and package coupling

The present work addresses the investigation of phase noise degradation of LC-tank VCOs due to realistic digitally originated substrate noise. The dominant mechanisms by which this noise is coupled to the output of the oscillator due to the substrate and the package are analyzed, indicating that both noise at low frequencies and at high frequencies around the oscillation fundamental significantly degrade phase noise.

Modeling and Evaluation of Substrate Noise Induced by Interconnects

Interconnects have deserved attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. In this paper, we evaluate the importance of interconnect-induced substrate noise. A known interconnect and substrate model is validated by comparing simulation results to experimental measurements. Based on the validated modeling approach, a complete study considering frequency, geometrical, load and shielding effects is presented The importance of interconnect-induced substrate noise is demonstrated after observing that, for typically sized interconnects and stale-of-the-art speeds, the amount of coupled noise is already comparable to that injected by hundreds of transistors.

Challenges for signal integrity prediction in the next decade

Abstract Noise caused by the activity of integrated circuits is a limiting factor for the development of future VLSI circuits. Transients of voltages and currents couple perturbations to the co-integrated circuits where the most effective medium to propagate noise is the silicon substrate. The effect is especially important where high-speed digital circuits are integrated together with highly sensitive analog sections, which is the case of modern communication transceivers. Taking into account the effect of noise during the circuit design requires a fine electrical modeling of the substrate and noise generation. The capability of substrate to propagate signals from DC to very high frequencies has to be understood and modeled, together with the role of doping profile and topology of doped regions (layout). In this tutorial paper the sources, propagation of noise and sensitivity of MOS circuits are presented and its trend in the next technology generations is evaluated. The challenges that modeling techniques and CAD tools have to face are commented, and the key points and more likely solutions are discussed.

A comparison between grounded and floating shield inductors for mmW VCOs

A floating-shield inductor implemented in CMOS process is compared with a conventional patterned ground shield inductor for the implementation of a LC voltage controlled oscillator (VCO) operating at mmW frequencies. In this work it is shown how the floating-shield inductor achieves higher quality factor and provides a better isolation for substrate-coupled high-frequency interferences.

Ground bounce modelling for digital gigascale integrated circuits

In the paper an analytical model for ground bounce noise taking into account the interdependence between switching current and noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. Noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes

A physical-based noise macromodel for fast simulation of switching noise generation

Efficient prediction of the substrate noise generated by large digital sections is currently a major challenge in System-on-a-Chip design. A macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel is generated from identification of the physical elements relevant to noise generation. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are proposed. Using this macromodel, prediction of the noise generated by large digital sections can be easily done following a methodology based on high-level logic simulation. As a first step to validation, the macromodel accuracy is demonstrated in some circuits consisting of a reduced number of gates.