Enrique Barajas

Low Noise Amplifiers for Low-Power Impulse-Radio Ultra Wide-Band Receivers

In this paper, two different low noise amplifiers (LNA) for impulse-radio (IR) ultra-wideband (UWB) receivers are presented. They have been designed in a 0.18 mum CMOS process, with a central frequency of 8 GHz and about 1 GHz bandwidth. The applications considered are portable applications for very short communication distances (body area networks, BAN) with bit rates up to 200 Mbps. Therefore, a crucial goal to achieve when designing the LNAs was power dissipation. In order to get very low power consumption, on/off switching technique has been implemented. Both LNAs are presented and analyzed, comparing their performances with state of the art LNAs

A Low-Power Template Generator for Coherent Impulse-Radio Ultra Wide-Band Receivers

In this paper, a template generator circuit for impulse-radio (IR) ultra wide-band (UWB) receivers is presented. The circuit is implemented in a 0.18 mum CMOS process. It is capable of generating a differential template signal having a four cycles long square waveform for both rising and falling edges of the input triggering signal. The template waveform cycle time is 125 ps. This allows the detection of UWB pulses whose energy is centered around 8 GHz. The unloaded peak-to-peak amplitude of the generated template waveform is 550 mV, and it is reduced to 230 mV when connected to a passive mixer. The average power consumption is 2.0 mW for a pulse repetition frequency (PRF) of 200 MHz. The presented template generator can be easily adapted to maximize the SNR for arbitrary received pulses

Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics

This work presents an experimental investigation about the relation between specific characteristics of a digital circuit (clock frequency and architecture) and the substrate noise spectrum that it generates. Both the discrete impulse train term and the continuous term of the substrate noise spectrum are investigated. The results indicate that the continuous term sets an upper bound to the substrate noise reduction that may be obtained by changing the digital frequency or by staggering the simultaneous activity of the circuit, two techniques that have been proposed in the literature to reduce substrate noise.

A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 µm CMOS

In this paper a 75 pJ/b all-digital quadrature coherent impulse radio ultra-wideband transceiver in 0.18 μm CMOS is presented. It consumes 42 mW operating at a 560 Mbps datarate. The receiver and transmitter share most of the components reducing the area. This design is optimal for low-power low-cost short-range high-speed communications.

Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.

Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems

This paper presents a behavioral model of a delay-locked loop (DLL) used to generate the timing signals in an integrated ultra wide-band (UWB) impulse radio (IR) system. The requirements of these timing signals in the context of UWB-IR systems are reviewed. The behavioral model includes a modeling of the various noise sources in the DLL that produce output jitter. The model is used to find the optimum loop filter capacitor value that minimizes output jitter. The accuracy of the behavioral model is validated by comparing the system level simulation results with transistor level simulations of the whole DLL.

Characterization and noise analysis of a 12-bit current steering digital-to-analog converter

This paper describes the process of characterizing a high-speed high-accuracy current steering digital-to-analog converter (DAC) and the study of the dI/dt noise in the power supply lines and the substrate noise generated by its operation.

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.

Design of a Broadband CMOS RF Power Amplifier to establish device-circuit aging correlations

This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation between the degradation of circuits RF performances and those of its individual devices parameters. The test structure, measurement set-up and procedure are described in detail.