Xiaomeng Shi

Equivalent circuit model of on-wafer CMOS interconnects for RFICs

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.

Sensitivity Analysis of Coupled Interconnects for RFIC Applications

This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters characterizing the coupled interconnects have been examined. The influence of the process parameters on transmission, reflection, near-end, and far-end crosstalk capacities of the coupled interconnects are discussed

Equivalent circuit model of on-wafer interconnects for CMOS RFICs

An equivalent circuit model of on-wafer interconnects was extracted directly from the S-parameter measurements. In the proposed model, the skin effect and the substrate losses have been considered. Furthermore, an additional element was introduced to predict the fringing effect for the first time. A hybrid genetic algorithm was used for the parameter extraction. The constructed two-/spl Pi/ model is computationally efficient and is shown to be sufficiently accurate for RF applications. The accuracy was demonstrated by the on-wafer measurements of interconnects with various physical dimensions, fabricated on the top-metal layer, employing a 0.18 /spl mu/m RF-CMOS process.

Sensitivity of on-wafer interconnects to CMOS process parameters at radio frequency

This paper investigates the sensitivity of the on-wafer interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. S-parameters of the interconnect have been examined. The influence of the process parameters on the transmission and reflection capacities of the on-wafer interconnects are discussed

Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two-pi blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed

Distortion of pulsed signals in carbon nanotube interconnects

This paper investigates the distortion of DC and radio frequency (RF) pulsed signals in carbon nanotube interconnects. A modified transmission line model for single-walled carbon nanotubes is employed for the simulation. Comparisons with the conventional AlCu interconnect are performed.

VLSI Architectures for Lifting-Based Discrete Wavelet Packet Transform

In this paper, dedicated hardware implementations for discrete wavelet packet transform (DWPT) are investigated. After an intensive review of the exiting DWPT architectures, a folded architecture for lifting-based DWPT is proposed. Based on the previous pipeline DWPT architecture, this folded architecture reduces the hardware complexity significantly by folding multilevel DWPT decomposition into a single configurable processing element (PE). Compared with the conventional single-PE DWPT architecture, this folded architecture does not require extra memory to buffer the intermediate data during the DWPT computation and therefore avoids intensive memory access. Circuit simulation and implementation results demonstrate that the proposed folded architecture computes the multilevel DWPT much faster than the conventional single-PE architecture, while the hardware cost of the two architectures are almost identical.

A 3.1-8 GHz CMOS UWB front-end receiver

A two-stage down-conversion architecture for 3.1–8 GHz ultra-wideband receiver front-end is designed which uses a local oscillator frequency equal to half the input frequency. The down-conversion technique is performed in two steps based on half-RF architecture to produce baseband signal. The proposed technique is implemented in 0.18 µm CMOS technology which achieves a conversion gain ranges from 36.1–32.4 dB and noise figure of 5.4–8.3 dB across the bandwidth.

Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.

Characterization of On-Wafer Vias for CMOS RFICs

Characterization of a single on-wafer via using a 0.18-mum RFCMOS technology is presented in this paper. The equivalent resistance and inductance of the via are extracted from full wave simulations up to 30 GHz frequency range. The de-embedding method is also discussed.