Beng Hwee Ong

Accurate and scalable RF interconnect model for silicon-based RFIC applications

A new figure of merit, intrinsic factor for interconnects, is proposed to provide insights as to how back-end metallization influences the performance of radio frequency integrated circuits. An accurate and scalable double-/spl pi/ radio frequency interconnect model, continuous across physical dimensions of width and length, is presented to demonstrate reliable predictions of interconnect characteristics up to 10 GHz. Using this interconnect model in gigahertz amplifier and voltage-controlled oscillator circuit simulations yields excellent correlations between simulated and on-wafer measured circuit results.

Equivalent circuit model of on-wafer interconnects for CMOS RFICs

An equivalent circuit model of on-wafer interconnects was extracted directly from the S-parameter measurements. In the proposed model, the skin effect and the substrate losses have been considered. Furthermore, an additional element was introduced to predict the fringing effect for the first time. A hybrid genetic algorithm was used for the parameter extraction. The constructed two-/spl Pi/ model is computationally efficient and is shown to be sufficiently accurate for RF applications. The accuracy was demonstrated by the on-wafer measurements of interconnects with various physical dimensions, fabricated on the top-metal layer, employing a 0.18 /spl mu/m RF-CMOS process.

A novel RFCMOS process monitoring test structure

A novel RFCMOS process monitoring test structure has been proposed for the first time in this paper. Excellent agreement in DC and RF characteristics has been observed between conventional test structures and the new process monitoring test structure for both n and p MOSFETs of different device dimensions. This new layout approach can be extended to other devices such as MIM capacitors, diodes, MOS varactors and interconnects.

Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.

Modeling and Layout Optimization Techniques for Silicon-Based Symmetrical Spiral Inductors

A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-ofis and optimization up to 10GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These flndings are particularly important when exploiting the cost-efiective silicon-based RF technologies for applications with operating frequencies greater than 2.5GHz.

Novel RF process monitoring test structure for silicon devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.

Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling

Various structures of on-wafer interconnect for CMOS RFICs fabricated by using 0.18um CMOS are investigated experimentally. The measured S-parameters in terms of the dimensions and frequencies are presented in the paper. Frequency dependence elements of interconnect is extracted from the measurement. A scalable physical model is derived and quantified using measurement results for straight top-metal interconnect.