Xingchao Yuan

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.

Design, modeling, and hardware correlation of a 3.2Gb/s/pair memory channel

With the rapid advance of silicon process technology, it is now possible to design input/output (I/O) circuits that operate at multigigabit data rates. As a result, accurate modeling and analysis of high-speed interconnect systems is essential to optimize the performance of the overall system. This paper describes the interconnect design, modeling, simulation, and characterization methodologies that are essential to achieve multigigabit data rates. It focuses on the physical layer verification and hardware correlation of functional systems and silicon to ensure robust system operation over 3.2Gb/s data rate using conventional low-cost packaging and printed circuit board (PCB) technologies. In order to capture conductor and dielectric losses, as well as other high-frequency effects of three-dimensional structures, accurate measurement-based simulation techniques that directly incorporate frequency-domain parameters from measurement or electromagnetic solver parameters into circuit simulation tools using fast Fourier transform (FFT) and bandlimiting windowing techniques are developed. Finally, simulation waveforms are correlated with prototypes at both component and system levels in both time and frequency domains.

Properties of mixed-mode parameters of cascaded balanced networks and their applications in modeling of differential interconnects

The cascading properties of general four-port networks are explored with respect to the standard to mixed-mode transformation of scattering matrices. Rigorous proofs are given to show that, for balanced networks, the odd-/even-mode scattering matrix of two cascaded networks equals the scattering matrix of the cascade of the respective odd-/even-mode networks. This concept is used to extract physical equivalent-circuit models for coupled backplane vias, differential package traces, and differentially routed data pins of XDR memory devices

Performance analysis and model-to-hardware correlation of multigigahertz parallel bus with transmit pre-emphasis equalization

The performance of multigigahertz systems is adversely impacted by nonideal physical effects such as attenuation, crosstalk, impedance mismatches, intersymbol interference, and component and parameter variations. Many of these nonideal physical effects can be mitigated by selecting proper signaling topologies and techniques, by using judicious design rules, and by applying advanced circuitry and signal processing techniques. However, the component and parameter variations due to process and environmental conditions are more difficult to overcome, and their impact on a multigigahertz system needs to be quantified in order to ensure robust system operation under worst case operating conditions. This paper investigates the sensitivity of the performance of multigigahertz systems to component and parameter variations using simulations. The modeling accuracy of the equalized channel is correlated with a prototype system operating at data rates of up to 8 Gb/s. The sensitivity of equalization taps to variations in channel parameters is also studied. Finally, a measurement-based simulation method of evaluating the impact of transmitter and receiver jitter on the system timing margin is presented.

Improved method for characterizing transmission lines using frequency-domain measurements

This work presents an improved and accurate methodology for extracting lossy frequency-dependent transmission parameters from S-parameter measurements. The presented technique first uses the multiline method to accurately determine the propagation constant. Then, it proposes a new approach to compute the characteristic impedance by determining the admittance first, based on the fact that the admittance can be modeled as a linear function of frequency. This process ensures both frequency dependent conductor and dielectric losses are accurately determined. It is demonstrated, through several practical examples, that the resulting transmission line parameter is free of common modeling errors at resonant frequencies.

EMI evaluation of a differential signaling interconnect at 3.2 Gbps

Differential signaling scheme has the inherent advantages of low electromagnetic interference (EMI) profile at multi-gigabits/s data rates. However, it is challenging to quantify the exact amount of EMI improvement due to the presence of other EMI sources in a realistic system. In this paper, we quantified the EMI benefit of a differential signaling system by using a test board characterized in a semianechoic chamber with pre-scan measurements. The test board contains an XDR/spl trade/ memory channel which uses differential signaling at 3.2 Gbps for data and single-ended signaling at 800 Mbps for command and address. It is measured in various operating modes and data patterns to differentiate the emissions from different sources such as clock nets, single ended signals, and differential signals. In addition, a near-field scanner is used to locate the EMI sources and/or antennas. The clock net is found to be the dominant source of EMI and the controller socket acted as the major EMI antenna. The high-speed differential data lines contribute to less than 1 dB of the overall EMI.

Electromagnetic modeling methodologies and design challenges of packages for 6.4-12.8 Gbps chip-to-chip interconnects

In order to predict and optimize the performance of high-speed digital systems, it Is essential to accurately model the interconnect systems. The traditional method of analyzing interconnects by decomposing the structure into subsections and representing them by circuit parameters calculated using quasistatic electromagnetic solvers loses accuracy at higher frequencies. Instead, it becomes increasingly important to use parameters obtained from full-wave analyses to determine the degradation of the interconnect performance due to 3D package structures. In this paper, the impact of packages on system performance is first discussed. Then, the unique design and modeling requirements and challenges for high-speed digital packages are described. This is followed by discussions on selection criteria of electromagnetic solvers and modeling methodologies. Several examples are presented to illustrate the success and limitations of the commercially available electromagnetic solvers. Future requirements of electromagnetic modeling for high-speed digital systems are also presented.

A robust physical model extraction method for a memory device with differential routed package traces

To quantify the impact of device parasitics on the performance and yield of high-speed systems, a reliable procedure for parasitic extraction and characterization needs to be established. A robust physical model extraction method of silicon parasitic is developed for a 3.2 Gbps memory device with differentially routed package traces. This method employs parasitic models that directly correlate to the physical features in the PCB, fixture, package, and the active device under proper voltage biases. Measurements are performed using a vector network analyzer (VNA) and a differential time-domain reflectometry (TDR). The standard two-port S-parameters are converted to the mixed-mode S-parameters, i.e., odd and even mode S-parameters. The model parameters of the parasitics are then extracted through the minimization of the difference between the simulated and the measured odd-mode S-parameters. Measured TDR results, such as package impedance and on-die termination resistance, are used to constrain the variables and optimization range. This method is applied to the parasitic extraction of an actual device to demonstrate its accuracy and robustness.