Ishtiaq Ahsan

Meeting critical gate linewidth control needs at the 65 nm node

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our teams success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Yield Learning Methodology in Early Technology Development

Yield learning during early technology development is critical to ensuring successful integration of new process technologies, meeting development schedules, and transitioning smoothly into manufacturing. However, yield learning in early technology development is very different from yield learning in manufacturing. This paper will discuss the unique challenges of yield learning in early technology development. To meet these challenges, innovative systematic and parametric yield models were developed to address many new issues that arose in early 45 nm development at IBM. Furthermore, to understand and characterize new yield loss mechanisms, innovative characterization methods were developed. This paper will illustrate the unified yield learning methodology in early technology development which combines these various yield models and methods to establish a grand pareto and a yield step-up plan to prioritize the whole technology development efforts.

Use of print-simulations in accelerated yield learning for 22nm BEOL technology

Back-end-of-line (BEOL) patterning defects on logic circuits are challenging to find and often involve lengthy wafer processing times and costly failure analysis resources to detect. A print-simulation tool was developed to predict patterning fails of such circuits. Validity of the simulator was verified independently through hardware data. Layout constructs of a functional logic circuit were simulated and potential weak spots that were susceptible to patterning fail were identified. Patterning solutions were put in place to address these fails. Independent test-structures were designed to electrically test for pattern fidelity of some of these constructs early in the process flow to provide faster feedback. Test results from these test-structures indicated that any potential gross patterning issues have been resolved for the identified design constructs before mask order. Yield learning methodologies like this significantly shortened the cycle of learning of the 22nm BEOL process.

Impact of intra-die thermal variation on accurate MOSFET gate-length measurement

It is known that significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions and the variation depends on the local pattern density of various types of exposed stacks of the wafer. This variation can create errors in the electrical measurement MOSFET gate length itself. Two electrical methods for measuring gate length will be discussed, namely, the resistive technique, where a long-wide poly-silicon resistor is used as a normalizing resistor; and the capacitive technique, where a long-wide plate gate capacitor is used as a normalizing capacitor. It is shown, that the capacitive technique is more immune to errors introduced by RTA driven intra-die thermal absorption variation. Methods of minimizing these measurement errors are briefly discussed.

Parametric composite limited yield index for functional circuits yield prediction

In this paper we present an early detection mechanism for semiconductor circuit yield prediction and tracking. Several discrete devices used as components of functional circuits have been examined by their first-metal level test data and correlated to the higher metal level functional yield. A concept of Device Health Composite Yield is also introduced in this paper.

Yield monitor for embedded-sige process optimization

If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early monitor of yield degradation due to eSiGe and therefore an effective vehicle for optimization between yield and performance. Using this monitoring structure, an eSiGe process optimized for yield was developed which does not show additional yield loss due to eSiGe while retaining comparable performance enhancements.